The semiconductor reference library

TPU v1 accelerator architecture

First-generation inference architecture with systolic matrix arithmetic, explicit buffers, and host-directed operations.

Acorn Computers

The Acorn organization credited with the processor design in VLSI’s ARM family manual.

AMD

AMD in the semiconductor source network. Explore its documented designs, technology and publications.

Arm

Arm in the semiconductor source network. Explore its documented designs, technology and publications.

GigaDevice

GigaDevice in the semiconductor source network. Explore its documented designs, technology and publications.

Google

Google in the semiconductor source network. Explore its documented designs, technology and publications.

Intel

Intel in the semiconductor source network. Explore its documented designs, technology and publications.

NVIDIA

NVIDIA in the semiconductor source network. Explore its documented designs, technology and publications.

TSMC

TSMC in the semiconductor source network. Explore its documented designs, technology and publications.

Arm Cortex-M3

Armv7-M processor core documented by ARM DDI 0337H; optional implementation features vary.

Complementary FET research structure

imec describes CFET as stacked nMOS and pMOS with monolithic and sequential integration schemes under research.

Discrete silicon-carbide MOSFET

Wolfspeed lists discrete SiC MOSFETs for power systems, with package and blocking-voltage filters.

FinFET logic transistor

A FinFET is contrasted with GAA by gate material on three channel sides.

Gate-all-around transistor

In a GAA transistor, gate material completely encircles the channel; imec reports Si GAA nMOS and pMOS research devices.

IBM 45-nm SOI CMOS technology

This IEDM 2006 implementation combines SOI CMOS, enhanced strain, immersion lithography and porous low-k back-end dielectrics. IBM reports functional 0.37 µm² SRAM cells and PFET/NFET saturation drive currents of 840/1240 µA per µm at 1.0 V. These are process demonstration results; the nominal 45 nm label is not a measurement of every transistor dimension.

Infineon BFP450

BFP450 is a surface-mount silicon NPN transistor for wideband RF amplification. Its datasheet separates minimum breakdown limits from typical small-signal gain and linearity. At 900 MHz, 3 V collector-emitter bias and 90 mA collector current, the reported maximum power gain is 23.5 dB while transducer gain is 19 dB. These metrics use different gain definitions; they must not be treated as interchangeable amplifier performance or as guaranteed values across frequency and bias.

Infineon IGC27T120T8L

A 1200 V trench and fieldstop IGBT supplied as bare die for power modules. The nominal 25 A rating assumes a packaged module at 100°C case temperature. Its 2.07 V maximum saturation voltage is a 25°C static on-wafer result; the separate 150°C specification is 2.25 V typical. These conditions prevent a misleading comparison between nominal current, absolute ratings and hot-junction behavior.

Infineon IRF7726

A commercial P-channel planar power MOSFET in a Micro-8 package. Its −30 V voltage limit and −7 A current rating describe different specified operating constraints; neither is a measured efficiency result. The 26 mΩ maximum on-resistance applies at −10 V gate drive, −7 A drain current and 25°C junction temperature.

Photodiode

Hamamatsu identifies Si/InGaAs photodiode families, arrays/modules, and light-position, imaging, spectrophotometry, and near-infrared applications.

Planar MOSFET structure

This educational cross-section diagram identifies the source, drain, gate, insulating layer and substrate of a MOSFET. It is a schematic, not a TEM or SEM micrograph, and it provides no measured process dimensions.

Power MOSFET

Infineon’s catalogue includes Si/SiC products, n/p-channel families, modules, bare die, and industrial/automotive contexts.

Power MOSFET package specimen

A photographed discrete power MOSFET in a through-hole package. The visible metal tab, package body and three leads show the external assembly. This photograph does not establish the internal cell structure, voltage rating or process technology.

Stacked-nanosheet GAA transistor

imec identifies vertically stacked nanosheets as a GAA implementation in scaling research.

Stacked-nanowire GAA transistor

imec reported vertically stacked-nanowire GAA research with Si nMOS/pMOS results; it is not a commercial product claim.

7nm Technology

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

Acorn Assembler Release 2 — Appendix D, ARM datasheet

Primary-source reference used for the bounded ARM2 fact review. Access and verification limits are recorded with the source.

Acorn RISC Machine Family Data Manual (1990)

Primary-source reference used for the bounded ARM2 fact review. Access and verification limits are recorded with the source.

AMD Announces Next-Generation Leadership Products at Computex 2019 Keynote

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

AMD Chiplet Architecture for High-Performance Server and Desktop Products

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

AMD Ryzen 5 3600 — Specifications

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

AMD ZEN 2 — Hot Chips 31

Source document cited by Museum technical exhibits. Only indexed excerpts were verified in this pass.

AMD Zen Core Architecture

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

An in-depth look at Google’s first Tensor Processing Unit (TPU)

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

Build and train machine learning models on our new Google Cloud TPUs

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

Computing without Clocks: Micropipelining the ARM Processor

Primary-source reference used for the bounded ARM2 fact review. Access and verification limits are recorded with the source.

Cortex-M3 Technical Reference Manual, ARM DDI 0337H

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

Evolution of GPUs

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

GD32F103CBT6 — Cortex-M3 with serial flash

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

GD32F103CBT6 Product Selector

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

GD32F103xx Datasheet, Revision 2.12

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

GeForce 8800 Architecture Technical Brief — The Classic GPU Pipeline: A Retrospective

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

iAPX 86/88/186/188 User’s Manual, 210912-001

Source document cited by Museum technical exhibits. Only indexed excerpts were verified in this pass.

In-Datacenter Performance Analysis of a Tensor Processing Unit

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

Intel 14 nm Technology Announcement (2014)

Original Intel presentation used to verify process dimensions; linked as a document reference.

Intel Microprocessor Quick Reference Guide — Product Family

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

Memory Component Handbook 1983 — AP-97A

Source document cited by Museum technical exhibits. Only indexed excerpts were verified in this pass.

NVIDIA GeForce 256 / NV10 — optical die specimen

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

NVIDIA Tech Demos — GeForce 256 entries

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

The 8086 Family Users Manual, October 1979

Source document cited by Museum technical exhibits. Only indexed excerpts were verified in this pass.

The Intel 8086 and the IBM PC

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

Tonight I’m Gonna Game Like It’s 1999!

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

TPU transformation: A look back at 10 years of our AI-specialized chips

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

What is x86 Architecture? A Primer to the Foundation of Modern Computing

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core

Source document cited by Museum technical exhibits. Follow the publisher or archive link to read the original.

Advantest V93000

A scalable SoC automated-test platform.

Applied Materials Catalyst CMP

Applied's CMP solution described for controlling copper dishing ahead of hybrid-bond annealing.

Applied Materials Mirra CMP

A 150/200 mm CMP family with integrated post-CMP cleaning options.

Applied Materials Producer CVD

A CVD platform for semiconductor film deposition across logic, DRAM, NAND and specialty applications.

ASM Intrepid ES

ASM's epitaxy tool for critical 300 mm transistor and memory applications.

ASML TWINSCAN NXE:3600D

ASML's 0.33-NA EUV scanner for 300 mm wafer exposure.

Axcelis Purion XE Series

A high-energy ion-implant family using RF LINAC beamline technology.

Canon FPA-5520iV

An i-line stepper for advanced-packaging lithography.

DISCO DAD3220

A single-spindle automatic dicing saw. DISCO marks production of this model as ended.

EUV lithography

EUV lithography transfers patterns using light with a wavelength of 13.5 nm. EUV systems print selected intricate layers; DUV systems remain part of the same manufacturing flow. Light wavelength should not be confused with a process node label or the final printed feature size.

EVG GEMINI FB

An automated system for collective die-to-wafer fusion and hybrid bonding in high-volume manufacturing.

Hitachi High-Tech GS1000

An electron-beam inspection/metrology system for wide-area semiconductor inspection.

KLA Surfscan SP2XP

KLA's unpatterned-wafer inspection system, documented for 45 nm generation requirements.

Lam Research Kiyo

Lam's conductor-etch family for electrically active device materials.

Nikon NSR-S635E

A 300 mm ArF immersion scanner with 1.35 NA.

Nova VeraFlex IV LE-XRF

An in-line materials-metrology tool combining XPS and low-energy XRF.

Onto Innovation Firefly G5

A panel-level packaging system combining automated inspection and 3D metrology.

SCREEN LA-3100

A flash-lamp annealer for millisecond thermal-dose control.

SCREEN SU-3400

A 300 mm single-wafer cleaner with a 24-chamber configuration.

Semiconductor metrology & inspection

Semiconductor metrology measures process features, while inspection looks for defects and other deviations. Applied Materials describes applications across FEOL and BEOL. A microscope image needs its method and specimen context before dimensions or failure mechanisms can be inferred.

TEL CLEAN TRACK LITHIUS Pro Z

TEL's 300 mm coater/developer for 10 nm and beyond process flows.

Teradyne UltraFLEXplus

A configurable semiconductor test platform with digital, RF, AC and DC instruments.

Veeco Lumina MOCVD

A Veeco MOCVD system based on TurboDisc technology for compound-semiconductor epitaxy.

Armv7-M

M-profile instruction-set architecture implemented by Cortex-M3.

x86

Instruction-set family originating with the Intel 8086; extensions must be tied to their own generations.

Silicon

Silicon is a semiconductor material used as the basis of many integrated circuits. A material, a wafer and a finished chip are different objects: follow their connections to see where each belongs.

High-bandwidth memory

HBM combines stacked DRAM dies with a wide interface for high-throughput data transfer. TSVs connect layers within a stack. Capacity, transfer rate and stacking details belong to a named generation and product; this overview does not assign one vendor’s specifications to every HBM device.

Memory module specimens

Three circuit boards show packaged memory devices and module connectors. Visible labels include Intel Flash and Micron and Samsung module markings. The Commons filename calls the image RAM chips, but the photograph includes different memory assemblies; it is not an HBM stack or a DRAM cell micrograph.

7 Series

80286

80386

80486

Acorn ARM2

The ARM2 implementation documented by Acorn: three pipeline stages and a 2 µm CMOS process. Introduction timing and unverified ISA/cache fields remain separate from checked facts.

Airmont

Akida

Alder Lake

Alpha 21064

Alpha 21164

Alpha 21264

Alpha 21364

Alpha 21464

Amber Lake

AMD Zen

CPU microarchitecture named by AMD for the original Ryzen desktop generation. Follow the linked product and manufacturer evidence.

Arctic Sound

ARM1

ARM10

ARM11

ARM250

ARM3

ARM6

ARM7

ARM8

ARM9

Au1

Bonnell

Broadwell

Bulldozer

Cannon Lake

Carmel

Cascade Lake

Celerity

Cell Broadband Engine Architecture

CHA

Chaberton

Chivano

Cloud AI 100

cnMIPS

Coffee Lake

Colossus

Comet Lake

Cooper Lake

Core

Cortex-A12

Cortex-A15

Cortex-A17

Cortex-A32

Cortex-A34

Cortex-A35

Cortex-A5

Cortex-A510

Cortex-A53

Cortex-A55

Cortex-A57

Cortex-A7

Cortex-A710

Cortex-A715

Cortex-A72

Cortex-A73

Cortex-A75

Cortex-A76

Cortex-A77

Cortex-A78

Cortex-A8

Cortex-A9

Cortex-M55

Cortex-X1

Cortex-X2

Cortex-X3

Denver

Diamond Rapids

Enhanced NetBurst

Esther

ET-Maxion

ET-Minion

Excavator

Exynos M1

Exynos M2

Exynos M3

Exynos M4

Exynos M5

Ezra

Falkor

Gaudi

Gen1

Gen10

Gen11

Gen12

Gen2

Gen3

Gen3.5

Gen4

Gen5

Gen5.75 (Ironlake)

Gen6

Gen7

Gen7.5

Gen8

Gen9

Gen9.5

Golden Cove

Goldmont

Goldmont Plus

Goya

Gracemont

Granite Rapids

Haswell

Hayes

Helios

Hexagon

Hunter

Hunter-ELP

Ice Lake (client)

Ice Lake (server)

Isaiah

Isaiah II

Ivy Bridge

Joshua

Jupiter Sound

K10

K5

K6

K6-2

K6-III

K7

K8

K9

Kaby Lake

Kittson

Knights Corner

Knights Ferry

Knights Hill

Knights Landing

Knights Mill

Knights Peak

Lake Crest

Lakefield

Larrabee

Logan

LuJiaZui

Machine Learning Processor (MLP)

Madison

Madison 9M

Mars I

Mars II

McKinley

Merced

Meteor Lake

MN-Core

Modified Pentium M

Montecito

Montvale

Navi

Nehalem

Nehemiah

Neoverse N1

Neoverse N2

Neoverse V1

NetBurst

NVDLA

Ocean Cove

P5

P6

Palm Cove

Penryn

Pentium M

Piledriver

Polaris

Polaris

Poseidon

Post-K

Poulson

POWER10

POWER11

POWER4

POWER5

POWER6

POWER6+

POWER7

POWER7+

POWER8

POWER8+

POWER9

Quicksilver

Raptor Lake

Rock Creek

Rocket Lake

Rosetta

Saltwell

Samuel

Samuel 2

Sandy Bridge (client)

Saphira

Sapphire Rapids

Sea Islands

Shadowcat

SHAVE v2.0

SHAVE v3.0 (Fragrak)

Silvermont

Skylake (client)

Skylake (server)

Skylark

Snow Ridge

Southern Islands

Spring Crest

Spring Hill

Steamroller

Storm

StrongARM

Sunny Cove

SX-Aurora

TaiShan v110

ThunderX1

Tiger Lake

Tremont

Triton

TSARLET

Tukwila

Vanilla-5

Vega

Volcanic Islands

Vulcan

Westmere

Whiskey Lake

Willow Cove

WuDaoKou

Xiaomi

z10

z12

z13

z14

z15

z196

z9

z900

z990

Zen 2

AMD CPU microarchitecture documented in its ISSCC 2020 core presentation; cache configuration varies by implementation.

Zen 3

Zen 4

Zen 5

Zen+

ZhangJiang

Apple M1 Ultra UltraFusion package

Apple packaging architecture joining two M1 Max dies with a silicon interposer.

LQFP48

48-pin low-profile quad flat package listed for GD32F103CBT6. This is a package class, not a unique die.

Hybrid bonding & TSMC SoIC

SoIC is TSMC’s platform for integrating chiplets in three dimensions. Its chiplet integration is distinct from a photograph of a finished package: the bonded interfaces and internal connections require their own evidence. The source explains wafer-on-wafer and chip-on-wafer integration options.

Federico Faggin

Federico Faggin led design work on the Intel 4004 project after Ted Hoff. Intel’s history credits Faggin, Hoff, Stan Mazor and Busicom’s Masatoshi Shima: the programmable processor emerged from a team and a calculator project.

Morris Chang

Morris Chang founded TSMC in 1987. The company’s own history frames its role around manufacturing customer-designed chips, connecting this founder’s story to the dedicated foundry business model.

Intel 14 nm (2014 disclosure)

Intel’s 2014 process uses second-generation tri-gate FinFETs. The manufacturer disclosed 42 nm fin pitch, 70 nm gate pitch and 52 nm interconnect pitch; these physical dimensions are distinct from the 14 nm generation name. Intel identified Core M as the first product manufactured on the process and reported volume production in August 2014. This entry describes that dated process implementation, without assigning those pitches to every later Intel 14 nm variant.

Samsung SF2

Samsung SF2 is a named foundry process. Its dated PPA claims retain the manufacturer’s own reference node and measurement conditions.

TSMC N2

TSMC N2 is a named foundry process. Its dated PPA claims retain the manufacturer’s own reference node and measurement conditions.

TSMC N7

TSMC 7nm FinFET process technology; distinct from the later N7+ EUV process.

Back end of line

Back end of line refers to the interconnect portion of wafer processing. Metrology and inspection are used across front-end and back-end-of-line applications. BEOL wiring should be distinguished from the later assembly, packaging and test stages.

Socket AM4

CPU socket specified for the complete Ryzen 5 3600 processor; not a bare-CCD package type.

Silicon wafer

A wafer is a thin semiconductor substrate on which multiple integrated circuits are built. This photograph shows the patterned surface of a 12-inch silicon wafer; its colors and visible patterns do not establish a process node or a specific chip identity.