MICROARCHITECTURE

POWER6+

Ibm microarchitectures power6+
Identity & fabrication
Architecture name

Scope: architecture

Source date: 2017-02-01

Source-reported parameter; source revision 2017-02-01. Not an independent measurement.

Foundry

Scope: architecture

Source date: 2017-02-01

Source-reported parameter; source revision 2017-02-01. Not an independent measurement.

Introduction

Scope: architecture

Source date: 2017-02-01

Source-reported parameter; source revision 2017-02-01. Not an independent measurement.

Process

Scope: architecture

Source date: 2017-02-01

Source-reported parameter; source revision 2017-02-01. Not an independent measurement.

Architecture predecessor

Scope: architecture

Source date: 2017-02-01

Source-reported parameter; source revision 2017-02-01. Not an independent measurement.

Architecture successor

Scope: architecture

Source date: 2017-02-01

Source-reported parameter; source revision 2017-02-01. Not an independent measurement.

CPU & clock domains
CPU execution type

Scope: architecture

Source date: 2017-02-01

Source-reported parameter; source revision 2017-02-01. Not an independent measurement.

Additional specifications
Designer

Scope: architecture

Source date: 2017-02-01

Source-reported parameter; source revision 2017-02-01. Not an independent measurement.

Help document this silicon.

We have not yet identified a reliable public visual source for this record. Suggest a die photograph, package image, paper or manufacturer diagram.

Sources and historical context

POWER6+ — ChipsWiki, revision 52538

ChipsWiki / WikiChip contributors · third-party-report · source linked