Vanilla-5

Umich microarchitectures vanilla-5

Specifications

8 SOURCE-LINKED FIELDS

Identity & fabrication
Architecture name	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-01-20 Source-reported parameter; source revision 2020-01-20. Not an independent measurement.
Foundry	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-01-20 Source-reported parameter; source revision 2020-01-20. Not an independent measurement.
Process	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-01-20 Source-reported parameter; source revision 2020-01-20. Not an independent measurement.
ISA	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-01-20 Source-reported parameter; source revision 2020-01-20. Not an independent measurement.
CPU & clock domains
CPU execution type	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-01-20 Source-reported parameter; source revision 2020-01-20. Not an independent measurement.
CPU pipeline stages	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-01-20 Source-reported parameter; source revision 2020-01-20. Not an independent measurement.
CPU decode width	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-01-20 Source-reported parameter; source revision 2020-01-20. Not an independent measurement.
Additional specifications
Designer	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-01-20 Source-reported parameter; source revision 2020-01-20. Not an independent measurement.

THE VISUAL EVIDENCE

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0 DOCUMENTED SOURCES

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Sources and historical context

Vanilla-5 — ChipsWiki, revision 4623

ChipsWiki / WikiChip contributors · third-party-report · source linked