DEVICE

IBM 45-nm SOI CMOS technology

This IEDM 2006 implementation combines SOI CMOS, enhanced strain, immersion lithography and porous low-k back-end dielectrics. IBM reports functional 0.37 µm² SRAM cells and PFET/NFET saturation drive currents of 840/1240 µA per µm at 1.0 V. These are process demonstration results; the nominal 45 nm label is not a measurement of every transistor dimension.

operating Family: SOI CMOS
substrate: silicon-on-insulator
integration: CMOS process with functional SRAM and porous low-k BEOL
application: high-performance CMOS
research Commercial: conference process demonstration

Specifications

8 SOURCE-LINKED FIELDS

Connectivity & devices
Device family	Manufacturer / primary sourceIBM Research Scope: process-variant Source date: 2006-12-01
Additional specifications
Substrate	Manufacturer / primary sourceIBM Research Scope: process-variant Source date: 2006-12-01
Application	Manufacturer / primary sourceIBM Research Scope: process-variant Source date: 2006-12-01
Ground-rule technology	Manufacturer / primary sourceIBM Research Scope: process-variant Source date: 2006-12-01
Supply voltage for reported Idsat	Manufacturer / primary sourceIBM Research Scope: process-variant Source date: 2006-12-01
PFET saturation drive current	Manufacturer / primary sourceIBM Research Scope: process-variant Conditions: VDD=1.0 V; 45 nm ground-rule technology Source date: 2006-12-01
NFET saturation drive current	Manufacturer / primary sourceIBM Research Scope: process-variant Conditions: VDD=1.0 V; 45 nm ground-rule technology Source date: 2006-12-01
Functional SRAM cell area	Manufacturer / primary sourceIBM Research Scope: process-variant Source date: 2006-12-01

THE VISUAL EVIDENCE

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Sources and historical context

High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography

IBM Research · official-disclosure · source linked