MICROARCHITECTURE

Saphira

Qualcomm microarchitectures saphira
Identity & fabrication
Architecture name

Scope: architecture

Source date: 2019-10-11

Source-reported parameter; source revision 2019-10-11. Not an independent measurement.

Foundry

Scope: architecture

Source date: 2019-10-11

Source-reported parameter; source revision 2019-10-11. Not an independent measurement.

ISA

Scope: architecture

Source date: 2019-10-11

Source-reported parameter; source revision 2019-10-11. Not an independent measurement.

Architecture predecessor

Scope: architecture

Source date: 2019-10-11

Source-reported parameter; source revision 2019-10-11. Not an independent measurement.

CPU & clock domains
CPU execution type

Scope: architecture

Source date: 2019-10-11

Source-reported parameter; source revision 2019-10-11. Not an independent measurement.

CPU execution type

Scope: type 2

Source date: 2019-10-11

Source-reported parameter; source revision 2019-10-11. Not an independent measurement.

CPU decode width

Scope: architecture

Source date: 2019-10-11

Source-reported parameter; source revision 2019-10-11. Not an independent measurement.

Cache hierarchy
L2 cache

Scope: duplex

Source date: 2019-10-11

Source-reported parameter; source revision 2019-10-11. Not an independent measurement.

L3 cache

Scope: block

Source date: 2019-10-11

Source-reported parameter; source revision 2019-10-11. Not an independent measurement.

Additional specifications
Designer

Scope: architecture

Source date: 2019-10-11

Source-reported parameter; source revision 2019-10-11. Not an independent measurement.

Help document this silicon.

We have not yet identified a reliable public visual source for this record. Suggest a die photograph, package image, paper or manufacturer diagram.

Sources and historical context

Saphira — ChipsWiki, revision 5908

ChipsWiki / WikiChip contributors · third-party-report · source linked