ARCHITECTURE

TPU v1 accelerator architecture

First-generation inference architecture with systolic matrix arithmetic, explicit buffers, and host-directed operations.

TPU v1 architecture

Specifications have not yet been established for this record.

Help document this silicon.

We have not yet identified a reliable public visual source for this record. Suggest a die photograph, package image, paper or manufacturer diagram.

Sources and historical context

In-Datacenter Performance Analysis of a Tensor Processing Unit

Norman P. Jouppi et al. / Google; ISCA 2017 ยท official-disclosure ยท publicly-readable

An in-depth look at Googleโ€™s first Tensor Processing Unit (TPU)

Google Cloud ยท official-disclosure ยท publicly-readable