Google TPU v1

Google’s historical account identifies TPU v1 as an application-specific processor first deployed internally in 2015 and focused on inference. This record therefore represents the first-generation accelerator, not every subsequent device called a TPU. Its purpose was to execute already-trained models within a larger computing service. The host system, model software, and request-handling infrastructure remain part of the complete application even when matrix arithmetic moves to dedicated silicon.

Google’s first-TPU explainer describes a 256 × 256 systolic matrix unit performing 8-bit integer multiply-and-accumulate work. Values move through neighbouring arithmetic units in a regular pattern, allowing reuse without returning every intermediate operation to a general register file. VLSI Museum interpretation: the central architectural resource is not merely a large count of multipliers. Their arrangement makes useful operand reuse possible, provided the workload can be mapped onto the array.

The ISCA paper describes weights arriving from external DRAM through a weight FIFO, while intermediate values reside in a 24 MiB on-chip Unified Buffer. DMA moves data between that buffer and host memory. Matrix operations write accumulators; activation instructions return results to the buffer. This is an explicitly managed flow of different data types, not a conventional CPU cache hierarchy. Sustaining arithmetic requires both weights and activations to arrive in time.

The paper identifies the original TPU as a 28nm implementation and its published floorplan gives substantial space to the Unified Buffer and matrix unit. VLSI Museum interpretation: storage is a first-order physical design concern in this accelerator. This packet links the paper’s disclosure without copying its figure or presenting it as optical photography. No Museum die photograph, transistor count, or foundry-specific process variant is asserted for this new record.

Google’s explainer emphasizes a minimal execution model without mechanisms such as branch prediction and out-of-order execution. VLSI Museum interpretation: restricting the supported computation can make scheduling more predictable, but does not imply that every neural network runs at peak arithmetic throughput. Matrix shape, reuse, transfers, and software organization still matter. A disclosed peak operation rate is a hardware capability under suitable conditions, not a universal requests-per-second guarantee for a deployed service.

Google’s May 2017 announcement describes second-generation TPUs for both training and inference and their introduction to Google Cloud. That provides a clear genealogy edge from v1 without erasing the change in purpose. VLSI Museum interpretation: later training capability belongs to the successor’s record, as do its memory and interconnect details. Using one TPU label for both generations would hide a major architectural and system-level expansion.