Zen 2

AMD CPU microarchitecture documented in its ISSCC 2020 core presentation; cache configuration varies by implementation.

Zen2Amd microarchitectures zen 2

Specifications

22 SOURCE-LINKED FIELDS

Identity & fabrication
Architecture name	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
Foundry	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
Foundry	Published analysisChipsWiki / WikiChip contributors Scope: manufacturer 2 Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
Introduction	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
Process	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
Process	Published analysisChipsWiki / WikiChip contributors Scope: process 2 Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
Process	Published analysisChipsWiki / WikiChip contributors Scope: process 3 Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
Architecture core count	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
ISA	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
Architecture predecessor	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
Architecture successor	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
CPU & clock domains
CPU execution type	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
CPU pipeline stages	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
CPU decode width	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
Additional specifications
Instruction-set family	Manufacturer / primary sourceAMD / ISSCC; uploaded by AMD Scope: architecture Source date: 2020
Desktop/server CCX cores	Manufacturer / primary sourceAMD / ISSCC; uploaded by AMD Scope: architecture Source date: 2020
Desktop/server L3 per CCX	Manufacturer / primary sourceAMD / ISSCC; uploaded by AMD Scope: architecture Source date: 2020
Designer	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
Core name	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
Core name	Published analysisChipsWiki / WikiChip contributors Scope: core name 2 Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
Core name	Published analysisChipsWiki / WikiChip contributors Scope: core name 3 Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.
Core name	Published analysisChipsWiki / WikiChip contributors Scope: core name 4 Source date: 2022-10-10 Source-reported parameter; source revision 2022-10-10. Not an independent measurement.

THE VISUAL EVIDENCE

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72 SOURCE-LINKED RELATIONSHIPS

ImplementationAMD Zen 2 CCDsilicon design

Slide 2 identifies the CCD and Zen 2 cores.

AMD / ISSCC; uploaded by AMD · Evidence

ImplementationAMD Ryzen 5 3600sku

Third-generation Ryzen Zen 2 family description and Ryzen 5 3600 row in product table.

AMD · Evidence

Documented organizationAMDcompany

Organization identified in the cited documentation; this edge does not imply foundry or packaging responsibility.

AMD / ISSCC; uploaded by AMD · Evidence

Referenced by · implements architectureEPYC 7232Psku