AMD Zen 2 CCD

AMD’s ISSCC chiplet presentation identifies a 74 mm², 7nm core-complex die and separately identifies client and server I/O dies. Its package diagrams place these components in Ryzen, EPYC, and Threadripper arrangements. The photographed CCD is therefore not the whole processor. External memory interfaces and package-level connections must be interpreted through the appropriate product’s I/O die and package, rather than assigned to this compute photograph.

AMD’s core presentation describes a four-core CCX with 16 MB of L3 in the desktop/server configuration and 512 KB of L2 per core. Its Hot Chips cache diagram places two CCXs in a CCD and identifies an Infinity Fabric die-to-die interface. The core presentation also shows smaller L3 configurations for other uses of Zen 2. VLSI Museum interpretation: a microarchitecture name does not imply one universal cache topology. The desktop/server CCD record must retain its own configuration, and software locality questions should start with the documented cache-sharing group.

AMD’s Zen 2 historical overview describes a new TAGE branch predictor, an operation cache enlarged to 4K operations, and floating-point datapaths widened to 256 bits. VLSI Museum interpretation: these changes address different parts of the work-supply chain. Prediction selects the path to fetch, the operation cache can supply previously decoded work, and execution width determines what that supplied work can do. Wider arithmetic alone cannot guarantee higher application throughput.

The ISSCC core disclosure describes repeated L3 slices, multiple stages of clock gating, and local regulators supplying the L2 and L3 arrays. These implementation details explain why doubling a cache is more than adding storage bits: clock distribution and memory-array supply must remain workable. This is vendor-documented implementation context; it does not establish the coordinates of those structures on the Museum’s particular optical photograph.

The Ryzen 5 3600 specification lists six enabled CPU cores, twelve threads, 32 MB of L3, an AM4 socket, and TSMC 7nm FinFET technology for its CPU cores. These values belong to the complete product. VLSI Museum interpretation: the socket describes the packaged processor’s platform connection, not a socket into which a bare CCD can be installed. Enabled product cores must also remain distinct from the reusable die design.

TSMC documents N7 as its 7nm FinFET technology entering volume production in 2018, and distinguishes N7+ as a later process using EUV lithography. That distinction prevents a generic seven-nanometre label from silently becoming an EUV claim. VLSI Museum interpretation: the linked foundry page establishes process-family context, while the AMD specification establishes this product’s stated CPU-core technology. An exact manufacturing variant needs its own explicit evidence.