MICROARCHITECTURE

Cortex-A32

Arm holdings microarchitectures cortex-a32
Identity & fabrication
Architecture name

Scope: architecture

Source date: 2020-04-07

Source-reported parameter; source revision 2020-04-07. Not an independent measurement.

Foundry

Scope: architecture

Source date: 2020-04-07

Source-reported parameter; source revision 2020-04-07. Not an independent measurement.

Introduction

Scope: architecture

Source date: 2020-04-07

Source-reported parameter; source revision 2020-04-07. Not an independent measurement.

ISA

Scope: architecture

Source date: 2020-04-07

Source-reported parameter; source revision 2020-04-07. Not an independent measurement.

Architecture predecessor

Scope: architecture

Source date: 2020-04-07

Source-reported parameter; source revision 2020-04-07. Not an independent measurement.

CPU & clock domains
CPU pipeline stages

Scope: architecture

Source date: 2020-04-07

Source-reported parameter; source revision 2020-04-07. Not an independent measurement.

Cache hierarchy
L2 cache

Scope: architecture scope

Source date: 2020-04-07

Source-reported parameter; source revision 2020-04-07. Not an independent measurement.

Additional specifications
Designer

Scope: architecture

Source date: 2020-04-07

Source-reported parameter; source revision 2020-04-07. Not an independent measurement.

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Sources and historical context

Cortex-A32 — ChipsWiki, revision 3790

ChipsWiki / WikiChip contributors · third-party-report · source linked