TSARLET

Cea-leti microarchitectures tsarlet

Specifications

13 SOURCE-LINKED FIELDS

Identity & fabrication
Architecture name	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-03-27 Source-reported parameter; source revision 2020-03-27. Not an independent measurement.
Foundry	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-03-27 Source-reported parameter; source revision 2020-03-27. Not an independent measurement.
Process	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-03-27 Source-reported parameter; source revision 2020-03-27. Not an independent measurement.
Process	Published analysisChipsWiki / WikiChip contributors Scope: process 2 Source date: 2020-03-27 Source-reported parameter; source revision 2020-03-27. Not an independent measurement.
Architecture core count	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-03-27 Source-reported parameter; source revision 2020-03-27. Not an independent measurement.
ISA	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-03-27 Source-reported parameter; source revision 2020-03-27. Not an independent measurement.
CPU & clock domains
CPU execution type	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-03-27 Source-reported parameter; source revision 2020-03-27. Not an independent measurement.
CPU execution type	Published analysisChipsWiki / WikiChip contributors Scope: type 2 Source date: 2020-03-27 Source-reported parameter; source revision 2020-03-27. Not an independent measurement.
CPU pipeline stages	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-03-27 Source-reported parameter; source revision 2020-03-27. Not an independent measurement.
CPU decode width	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-03-27 Source-reported parameter; source revision 2020-03-27. Not an independent measurement.
Cache hierarchy
L2 cache	Published analysisChipsWiki / WikiChip contributors Scope: cluster Source date: 2020-03-27 Source-reported parameter; source revision 2020-03-27. Not an independent measurement.
L3 cache	Published analysisChipsWiki / WikiChip contributors Scope: cluster Source date: 2020-03-27 Source-reported parameter; source revision 2020-03-27. Not an independent measurement.
Additional specifications
Designer	Published analysisChipsWiki / WikiChip contributors Scope: architecture Source date: 2020-03-27 Source-reported parameter; source revision 2020-03-27. Not an independent measurement.

THE VISUAL EVIDENCE

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Sources and historical context

TSARLET — ChipsWiki, revision 3846

ChipsWiki / WikiChip contributors · third-party-report · source linked