MICROARCHITECTURE

Acorn ARM2

The ARM2 implementation documented by Acorn: three pipeline stages and a 2 µm CMOS process. Introduction timing and unverified ISA/cache fields remain separate from checked facts.

ARM2ARM 2Acorn microarchitectures arm2
Identity & fabrication
Process
Matching source values (1)

2 µm · ChipsWiki / WikiChip contributors
Acorn/microarchitectures/arm2 · revision 17582 · {{microarchitecture}} / process · Shared upstream; not independent confirmation.

Scope: architecture

Source date: 1995

Only this archived field was corroborated; see source-specific verification limits.

Introduction date

Scope: architecture

Archived value 1986 is retained in recovery evidence but remains uncorroborated. The author’s 1987 first-sample date describes a different event.

Architecture name

Scope: architecture

Source date: 2018-07-10

Source-reported parameter; source revision 2018-07-10. Not an independent measurement.

Foundry

Scope: architecture

Source date: 2018-07-10

Source-reported parameter; source revision 2018-07-10. Not an independent measurement.

Foundry

Scope: manufacturer 2

Source date: 2018-07-10

Source-reported parameter; source revision 2018-07-10. Not an independent measurement.

Introduction

Scope: architecture

Source date: 2018-07-10

Source-reported parameter; source revision 2018-07-10. Not an independent measurement.

Architecture core count

Scope: architecture

Source date: 2018-07-10

Source-reported parameter; source revision 2018-07-10. Not an independent measurement.

ISA

Scope: architecture

Source date: 2018-07-10

Source-reported parameter; source revision 2018-07-10. Not an independent measurement.

Architecture predecessor

Scope: architecture

Source date: 2018-07-10

Source-reported parameter; source revision 2018-07-10. Not an independent measurement.

Architecture successor

Scope: architecture

Source date: 2018-07-10

Source-reported parameter; source revision 2018-07-10. Not an independent measurement.

CPU & clock domains
CPU execution type

Scope: architecture

Source date: 2018-07-10

Source-reported parameter; source revision 2018-07-10. Not an independent measurement.

CPU execution type

Scope: type 2

Source date: 2018-07-10

Source-reported parameter; source revision 2018-07-10. Not an independent measurement.

CPU pipeline stages

Scope: architecture

Source date: 2018-07-10

Source-reported parameter; source revision 2018-07-10. Not an independent measurement.

CPU decode width

Scope: architecture

Source date: 2018-07-10

Source-reported parameter; source revision 2018-07-10. Not an independent measurement.

Additional specifications
Designer
Matching source values (1)

Acorn Computers · ChipsWiki / WikiChip contributors
Acorn/microarchitectures/arm2 · revision 17582 · {{microarchitecture}} / designer · Shared upstream; not independent confirmation.

Scope: architecture

Source date: 1990

Only this archived field was corroborated; see source-specific verification limits.

Pipeline stages

Scope: architecture

Only this archived field was corroborated; see source-specific verification limits.

First functional samples (author account)

Scope: architecture

Source date: 1995

Sample delivery year in Furber’s retrospective; not a verified product introduction date.

Help document this silicon.

We have not yet identified a reliable public visual source for this record. Suggest a die photograph, package image, paper or manufacturer diagram.

TECHNICAL ARTICLE

ARM2: a short pipeline and a careful historical record

Three corroborated archive fields, with unresolved claims left visible.

Overlapping three stages

Acorn’s ARM2 datasheet extract describes one instruction executing while following instructions are decoded and fetched. VLSI’s manual explicitly names three stages. This explains overlap between instructions; it does not establish a fixed completion rate for every instruction or memory access.

Samples and introduction are different events

Steve Furber’s retrospective describes ARM2’s move to 2 µm CMOS and functional samples in 1987. The archived WikiChip infobox says introduction in 1986. Museum interpretation: these event labels require separate evidence, so the introduction date stays unresolved rather than being replaced automatically.

Follow the documented connections

Sources and historical context

ARM2 - Microarchitectures - Acorn (archived WikiChip)

WikiChip contributors · Internet Archive capture · third-party-report · archive-identity-verified; facts require separate corroboration

ORIGINAL PAGE
ARM2 - Microarchitectures - Acorn
ARCHIVE CAPTURE
20201124125451
VERIFICATION
archive-verified · MediaWiki title / page id / revision; scalar infobox rows identified by their field labels
Acorn RISC Machine Family Data Manual (1990)

VLSI Technology, Inc.; original manual scan hosted by Bitsavers · official-disclosure · Indexed original-scan excerpts checked: Preface p. ix and Introduction p. 1-8. Full PDF retrieval was unavailable; no manual images acquired.

Acorn Assembler Release 2 — Appendix D, ARM datasheet

Acorn Computers; original manual scan hosted by 4corn · official-disclosure · Indexed scan text checked at printed p. 191: explicitly ARM2, with reference to VL86C010. Full PDF exceeded browser size limit; publication year not verified.

Computing without Clocks: Micropipelining the ARM Processor

Steve Furber; Springer-Verlag London (1995); author copy hosted by ResearchGate · third-party-report · Author-uploaded text checked in section 5; uploader attribution to Steve Furber visible. Publisher identity and 1995 date confirmed at https://link.springer.com/chapter/10.1007/978-1-4471-3575-3_5 . Primary participant account, not a contemporaneous release notice. No reuse grant asserted.

ARM2 — ChipsWiki, revision 17582

ChipsWiki / WikiChip contributors · third-party-report · source linked