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PROCESS

Intel 14 nm (2014 disclosure)

Intel’s 2014 process uses second-generation tri-gate FinFETs. The manufacturer disclosed 42 nm fin pitch, 70 nm gate pitch and 52 nm interconnect pitch; these physical dimensions are distinct from the 14 nm generation name. Intel identified Core M as the first product manufactured on the process and reported volume production in August 2014. This entry describes that dated process implementation, without assigning those pitches to every later Intel 14 nm variant.

Intel 14nmIntel 14 nm process
operating Family
logic CMOS
gate Geometry
FinFET / tri-gate
integration
commercial process implementation
application
Core M / Broadwell
research Commercial
volume production reported 2014-08-11

Specifications

6 SOURCE-LINKED FIELDS
Packaging, power & physical analysis
Reported SRAM cell area
Manufacturer / primary sourceIntel

Scope: process-variant

Source date: 2014-08-11

Intel’s 2014 disclosure; not a universal value for every vendor or later 14 nm process variant.

Transistor structure
Manufacturer / primary sourceIntel

Scope: process-variant

Source date: 2014-08-11

Additional specifications
Fin pitch
Manufacturer / primary sourceIntel

Scope: process-variant

Source date: 2014-08-11

Intel’s 2014 disclosure; not a universal value for every vendor or later 14 nm process variant.

Gate pitch
Manufacturer / primary sourceIntel

Scope: process-variant

Source date: 2014-08-11

Intel’s 2014 disclosure; not a universal value for every vendor or later 14 nm process variant.

Interconnect pitch
Manufacturer / primary sourceIntel

Scope: process-variant

Source date: 2014-08-11

Intel’s 2014 disclosure; not a universal value for every vendor or later 14 nm process variant.

Fin height
Manufacturer / primary sourceIntel

Scope: Intel 2014 14 nm process disclosure

Source date: 2014-08-11

THE VISUAL EVIDENCE

Visual sources

0 DOCUMENTED SOURCES

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TECHNICAL ARTICLE

Intel 14 nm: a process name and several physical dimensions

Keep the manufacturer’s process scope attached to every number.

VLSI Museum synthesis of the cited sources. · 2026-09-07

Several dimensions coexist

Intel reported 42 nm fin pitch, 70 nm gate pitch and 52 nm interconnect pitch. Museum interpretation: a process name cannot substitute for the particular dimension a comparison requires.

PRIMARY SOURCEIntel

A specific manufacturer and generation

The August 2014 release identifies Intel’s second generation of tri-gate transistors. This record describes that disclosed process; it does not assign Intel’s dimensions to another foundry or to all later variants.

PRIMARY SOURCEIntel
Follow the documented connections

Follow the connections

3 SOURCE-LINKED RELATIONSHIPS

Sources and historical context

Intel 14 nm Technology Announcement — Mark Bohr, 11 August 2014

Intel · official-disclosure · Presentation text checked at PDF pages 14, 15, 23 and 37 (one-based); source linked, slides and photographs not republished.

Intel discloses 14 nm manufacturing process technical details

Intel · official-disclosure · Official release and date checked; linked package photo credits Business Wire and remains unacquired.