MICROARCHITECTURE

Denver

Nvidia microarchitectures denver
Identity & fabrication
Architecture name

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

Foundry

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

Introduction

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

Process

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

Process

Scope: process 2

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

Architecture core count

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

ISA

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

Architecture successor

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

CPU & clock domains
CPU execution type

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

CPU decode width

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

Cache hierarchy
L2 cache

Scope: cluster

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

L1 cache

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

L1 instruction cache

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

L1 instruction organization

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

L1 instruction associativity

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

L1 data cache

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

L1 data organization

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

L1 data associativity

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

L2 organization

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

L2 associativity

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

Additional specifications
Designer

Scope: architecture

Source date: 2020-02-11

Source-reported parameter; source revision 2020-02-11. Not an independent measurement.

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Sources and historical context

Denver — ChipsWiki, revision 4341

ChipsWiki / WikiChip contributors · third-party-report · source linked