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SEMICONDUCTOR REFERENCE

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Find products, devices, processes and manufacturing tools with specifications and original sources.

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8 records

material

Vendor PPA claims retain their own reference process and conditions. Node labels are not physical gate dimensions. Missing fields are unresearched; conflicting observations remain visible.
CompareEntityMaterial / stageApplicationTechnology
SiliconIndustry · concept
unresearchedunresearchedunresearched

wafer

Vendor PPA claims retain their own reference process and conditions. Node labels are not physical gate dimensions. Missing fields are unresearched; conflicting observations remain visible.
CompareEntityMaterial / stageApplicationTechnology
Silicon waferIndustry · concept
unresearchedunresearchedunresearched

process stage

Vendor PPA claims retain their own reference process and conditions. Node labels are not physical gate dimensions. Missing fields are unresearched; conflicting observations remain visible.
CompareEntityMaterial / stageApplicationTechnology
Back end of lineIndustry · concept
unresearchedunresearchedunresearched

process

Vendor PPA claims retain their own reference process and conditions. Node labels are not physical gate dimensions. Missing fields are unresearched; conflicting observations remain visible.
CompareEntityTransistor integrationPerformance claimPower claimDensity definitionPPA baseline
TSMC N7TSMC · process variant
unresearchedunresearchedunresearchedunresearchedunresearched
Intel 14 nm (2014 disclosure)Intel · process variant · 2014
Second-generation tri-gate (FinFET)Transistor structureunresearchedunresearchedunresearchedunresearched
TSMC N2TSMC · process variant
NanosheetTransistor architecture10–15 %Performance improvement25–30 %Power reductionnot foundTSMC N3 (2022 disclosure)PPA baseline
Samsung SF2Samsung · process variant
GAATransistor architecture12 %Performance improvement25 %Power efficiency improvementunresearchedSamsung SF3 (2023 disclosure)PPA baseline

soi cmos

Source values retain units and entity scope. Open the citation on the record for conditions. Missing fields are unresearched; conflicting observations remain visible.
CompareEntityDevice familyGate geometryMaterial / substratePolarity / configurationApplication
IBM 45-nm SOI CMOS technologyIBM · process variant · 2006
SOI CMOSDevice familyunresearchedsilicon-on-insulatorSubstrateunresearchedhigh-performance CMOSApplication

Compare specifications

Source values, conditions and entity scope stay together.

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Cross-foundry PPA is not directly comparable: each vendor uses a different reference node, test design and density definition. Percentage improvements below do not identify a winner.

Specification / evidenceTSMC N2process-variant
Transistor architecture
official-disclosure · sourcedScope: process-variantSource date: 2022-06-17Source ↗
PPA baseline
official-disclosure · sourcedScope: process-variantSource date: 2022-06-17Source ↗
Performance improvement
official-disclosure · sourcedScope: process-variantBaseline: TSMC N3 (2022 disclosure)Conditions: Same power; test design and operating point not specified in release.Source date: 2022-06-17Source ↗
Power reduction
official-disclosure · sourcedScope: process-variantBaseline: TSMC N3 (2022 disclosure)Conditions: Same speed; test design and operating point not specified in release.Source date: 2022-06-17Source ↗
Density definition
official-disclosure · not-foundScope: process-variantSource date: 2022-06-17Not found in this checked release; does not claim universal non-disclosure.Source ↗
Production status
official-disclosure · sourcedScope: N2Conditions: Vendor statement read 2026-09-14; page has no publication date.Source ↗

Measured benchmarks must include workload/version, configuration, power mode and date. Theoretical peaks and vendor claims are not measured benchmark results.

Samsung SF2 / TSMC N2 — PPA and reference conditions