VLSI Korea
Workload and traffic model
Build a traffic matrix across the documented CPU, graphics, AI and I/O engines. Model concurrent bursts, locality and worst-case response time at shared memory before choosing arbitration or buffering.
SAMSUNG / SILICON DESIGN
Samsung Exynos 2600
A source-based tour from the C1 CPU tiers to the package, with official capabilities separated from kernel-derived analysis.
Samsung Exynos 2600 DIE PHOTOGRAPH
Image courtesy of Chipwise ·Used with permission· Die photograph · Resized and format-converted for display; original image content and watermarks preserved.
Origin & contributions
Original source · Retrieved 2026-09-09
Chipwise / NanoPhysics · photographer · Included in this image
Image courtesy of Chipwise · Used with permission. Link the original Chipwise source page and retain its markings and credits. Permission reported by the Museum operator on 2026-09-09. Display resizing and format conversion only; no removal of annotations or watermarks. No onward redistribution or comparison-export licence is granted by the Museum.
Samsung Exynos 2600 SoC. Frontside die view, as identified by source
Source photography; preparation and visible markings are preserved. This photograph supplies no independently verified geometric measurements.
Specifications
45 SOURCE-LINKED FIELDS| Identity & fabrication | |
|---|---|
| Year | Manufacturer / primary sourceSamsung Scope: silicon-die Source date: 2025-12-18 Year identifies first public introduction where a dated launch is available; see record notes for exceptions. |
| Process | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die Samsung process designation; not a measured gate dimension. |
| Foundry | Published analysisKurnal Insights Scope: silicon-die Source date: 2026-05-29 Independent analyst attribution. |
| Product status | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die Status on the manufacturer page as accessed on 2026-09-09. |
| CPU & clock domains | |
| CPU architecture | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| CPU cores | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| CPU configuration | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| CPU prime core | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| CPU performance cores | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| CPU efficiency-oriented cores | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| CPU matrix extension | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| Graphics | |
| GPU | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| GPU features | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| ENSS techniques | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| AI & security | |
| NPU configuration | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die Array configuration. MAC count is not a TOPS rating without precision, clock and operation-count conventions. |
| AI deployment | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| Security | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| Memory & interfaces | |
| Memory | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| Storage | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| Camera, video & display | |
| Display | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| Maximum camera resolution | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die ISP capability; actual phone sensor resolution is device-specific. |
| Single-camera processing | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| Dual-camera processing | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| ISP features | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| Video encoding | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| Video decoding | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die |
| Video codecs | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die Codec support list; the page does not assign every codec to every listed encode/decode mode. |
| Connectivity & devices | |
| Documented devices | Manufacturer / primary sourceSamsung Newsroom Scope: silicon-die Source date: 2026-02-26 This launch table establishes Singapore variants; other markets can use different processors. |
| Device availability | Manufacturer / primary sourceSamsung Newsroom Scope: silicon-die Source date: 2026-02-26 Singapore general availability; distinct from the chip introduction in 2025. |
| Device connectivity | Manufacturer / primary sourceSamsung Newsroom Scope: silicon-die Source date: 2026-02-26 Device-level specifications, not proof that Wi-Fi or Bluetooth radios are integrated on this SoC. |
| Packaging, power & physical analysis | |
| Reported die width | Published analysisKurnal Insights Scope: silicon-die Source date: 2026-05-29 Original analyst catalog value. Public entry gives dimensions but does not document calibration, die boundary convention, specimen provenance or uncertainty. |
| Reported die height | Published analysisKurnal Insights Scope: silicon-die Source date: 2026-05-29 Original analyst catalog value. Public entry gives dimensions but does not document calibration, die boundary convention, specimen provenance or uncertainty. |
| Reported die area | Published analysisKurnal Insights Scope: silicon-die Source date: 2026-05-29 Original analyst catalog value. Public entry gives dimensions but does not document calibration, die boundary convention, specimen provenance or uncertainty. |
| Verified die geometry | UnconfirmedSamsung Scope: silicon-die Source date: 2025-12-18 No source meeting calibrated geometry requirements accepted in this scout pass. Reported measurements, if present, remain separately labeled. |
| Thermal packaging | Manufacturer / primary sourceSamsung Semiconductor Scope: silicon-die EMC: epoxy molding compound. Samsung describes high-k EMC in the heat-dissipation context. |
| Reported CPU scheduler groups | Published analysisgamma0burst Scope: silicon-die Source date: 2026-03-25 Kernel-derived report; the two low-frequency C1-Pro groups appear as six cores in the official 1 + 3 + 6 specification. |
| Reported GPU organization | Published analysisgamma0burst Scope: silicon-die Source date: 2026-03-25 Reported kernel configuration; shader-lane, TMU and ROP counts remain unverified. |
| Reported GPU frequency range | Published analysisgamma0burst Scope: silicon-die Source date: 2026-03-25 Reported operating table, not guaranteed sustained frequency. |
| Reported NPU organization | Published analysisgamma0burst Scope: silicon-die Source date: 2026-03-25 |
| Reported modem pairing | Published analysisgamma0burst Scope: silicon-die Source date: 2026-03-25 The analyst reports an S5410 pairing and no integrated-modem entry in the examined kernel. |
| Estimated CPU complex area | Published analysisReptalica Scope: silicon-die Source date: 2026-04-25 Die-photo annotation; calibration and block-boundary uncertainty are not established. Original post text was accessible through the Vengineer embed. |
| Estimated GPU complex area | Published analysisReptalica Scope: silicon-die Source date: 2026-04-25 Die-photo annotation; calibration and block-boundary uncertainty are not established. Original post text was accessible through the Vengineer embed. |
| Estimated NPU complex area | Published analysisReptalica Scope: silicon-die Source date: 2026-04-25 Die-photo annotation; calibration and block-boundary uncertainty are not established. Original post text was accessible through the Vengineer embed. |
| Estimated SLC + tags area | Published analysisReptalica Scope: silicon-die Source date: 2026-04-25 Die-photo annotation; calibration and block-boundary uncertainty are not established. Original post text was accessible through the Vengineer embed. |
| Reported LPDDR5X PHY regions | Published analysisReptalica Scope: silicon-die Source date: 2026-04-25 An annotated region count does not establish aggregate bus width or package routing. |
With an engineering storyEditorial update
ARCHITECTURE → RTL → GDS
All design guides ↗Design with this record
Start with documented specifications, then use the study prompts below. The prompts are engineering guidance, not a claim about this product’s private RTL or physical implementation.
- CPU cores
- Samsung Semiconductor ↗
- Process
- Samsung Semiconductor ↗
- Memory
- Samsung Semiconductor ↗
- Storage
- Samsung Semiconductor ↗
- NPU configuration
- Samsung Semiconductor ↗
- Reported die area
- Kurnal Insights ↗
Contracts before RTL
Choose a representative producer/consumer path and specify acceptance, ordering, backpressure, outstanding capacity and reset recovery. Turn these contracts into assertions and test scenarios before optimizing the datapath.
A feasible physical plan
Obtain macro abstracts, pin maps, timing libraries and activity-based power estimates. Explore macro proximity, routing channels and power-grid reachability together. An annotated die photograph can suggest study questions, but cannot supply a netlist, PDK or signoff constraints.
TECHNICAL ARTICLE
Exynos 2600: CPU, AI, imaging and the heat path
A source-based tour from the C1 CPU tiers to the package, with official capabilities separated from kernel-derived analysis.
Ten cores, three performance tiers
Samsung groups the CPU as one C1-Ultra, three faster C1-Pro cores and six efficiency-oriented C1-Pro cores. The smaller Cortex-A520 class used in Exynos 2500 is replaced by C1-Pro cores. SME2 adds matrix instructions for CPU-side machine learning; it is separate from the dedicated NPU.
PRIMARY SOURCESamsung Semiconductor
AI execution and a secure boot path
The NPU specification is 32K MAC. Samsung also supports ExecuTorch for bringing PyTorch models to its on-device runtime. Virtualization security and hybrid post-quantum cryptography beginning in ROM address isolation and software verification. The MAC figure alone does not establish comparable TOPS.
PRIMARY SOURCESamsung Semiconductor
Rendering, reconstruction and frame generation
Xclipse 960 combines ray tracing with ENSS neural upscaling and frame generation. Rendering more frames, reconstructing a higher-resolution image and generating intermediate frames are different workloads, so Samsung’s separate graphics improvement figures should not be combined into one native-rendering speedup.
PRIMARY SOURCESamsung Semiconductor
From sensor input to video output
VPS analyzes scene content and DVNR reduces noise in low-light video. The ISP accepts sensors up to 320 MP, while the documented real-time modes include 108 MP at 30 fps and dual 64 MP + 32 MP input. The media block separately lists 8K30 encoding, 8K60 decoding and APV support.
PRIMARY SOURCESamsung Semiconductor
A package designed around the heat path
The Heat Path Block and high-k epoxy molding compound improve the package’s heat-transfer path. This is a package-level design claim: a die photograph does not show the complete stack or the phone’s cooling assembly. Sustained performance also depends on that surrounding system.
PRIMARY SOURCESamsung Semiconductor
Read the improvement figures with their baseline
Samsung reports up to 39% higher CPU performance, 113% higher generative-AI performance, twice the GPU compute performance and up to 50% better ray tracing versus Exynos 2500. Its other internal-test claims include up to 3× smoother ENSS output, 50% lower ISP power and 16% lower thermal resistance. These are manufacturer test results with workload and environment limitations, not Museum measurements.
PRIMARY SOURCESamsung Semiconductor
What kernel analysis adds
gamma0burst reports a 1+3+3+3 CPU grouping and an eight-WGP GPU configuration from Galaxy S26 kernel material. These software descriptions add detail to the official specifications, but do not locate blocks on the die or establish a complete interconnect graph.
PUBLISHED ANALYSISgamma0burst
Chip capability and shipping devices
Samsung’s Singapore launch table identifies Exynos 2600 in Galaxy S26 and S26+, available from March 11, 2026. Its Bluetooth entries differ between the two phones. Device connectivity, camera sensors and installed memory describe a shipping product configuration; they should not all be attributed to blocks integrated on the application-processor die.
PRIMARY SOURCESamsung Newsroom
Reading areas and interfaces from a die photograph
Reptalica’s annotations, embedded in Vengineer’s article, estimate CPU, GPU and NPU complex areas. Vengineer highlights the changed placement of the LPDDR PHY regions and asks how they connect through the package. These are useful analysis leads; exact boundaries, calibration and package routing remain unresolved.
Reference IP is a guide, not a verified floorplan
Arm describes C1-DSU as managing coherency and memory across C1 CPU clusters, and SI L1 as combining coherent interconnect, a non-coherent NoC and an optional system cache. These documents explain the roles such blocks can play. They do not verify Exynos 2600’s exact NoC, cache capacity, connectivity graph or physical placement.
Follow the connections
2 SOURCE-LINKED RELATIONSHIPSProduct-series membership; does not assert shared masks or identical silicon.
Samsung · EvidenceSamsung footnote 1 names Exynos 2500 as predecessor.
Samsung · EvidenceTHE VISUAL EVIDENCE
6 DOCUMENTED SOURCESVisual sources
Die photographs shared by their authors on X. Open a post to explore its images and discussion.
Die photograph · X
Samsung Exynos 2600 — annotated Chipwise die photograph
Hosted image provenance · 5
TEM imageHosted in Museum
Samsung Exynos 2600 — TEM image
Chipwise / NanoPhysics
700 × 499 pxTechnical archive / analysis
Samsung Exynos 2600. STEM/TEM micrograph; exact acquisition mode from source caption or image strip
View original visual sourceRights, provenance & link history
- Rights status
- PERMISSION GRANTED
- Local hosting / thumbnails / hotlinking
- Allowed / Allowed / Not enabled
- Attribution
- Image courtesy of Chipwise · Used with permission
- Identity / confidence
- matched / high
- Evidence reviewed
- 2026-09-09
- Link checked
- 2026-09-09 · ok · HTTP 200
Access to a source does not grant permission to reproduce its images.
TEM imageHosted in Museum
Samsung Exynos 2600 — TEM image
Chipwise / NanoPhysics
700 × 499 pxTechnical archive / analysis
Samsung Exynos 2600. STEM/TEM micrograph; exact acquisition mode from source caption or image strip
View original visual sourceRights, provenance & link history
- Rights status
- PERMISSION GRANTED
- Local hosting / thumbnails / hotlinking
- Allowed / Allowed / Not enabled
- Attribution
- Image courtesy of Chipwise · Used with permission
- Identity / confidence
- matched / high
- Evidence reviewed
- 2026-09-09
- Link checked
- 2026-09-09 · ok · HTTP 200
Access to a source does not grant permission to reproduce its images.
TEM imageHosted in Museum
Samsung Exynos 2600 — TEM image
Chipwise / NanoPhysics
700 × 499 pxTechnical archive / analysis
Samsung Exynos 2600. STEM/TEM micrograph; exact acquisition mode from source caption or image strip
View original visual sourceRights, provenance & link history
- Rights status
- PERMISSION GRANTED
- Local hosting / thumbnails / hotlinking
- Allowed / Allowed / Not enabled
- Attribution
- Image courtesy of Chipwise · Used with permission
- Identity / confidence
- matched / high
- Evidence reviewed
- 2026-09-09
- Link checked
- 2026-09-09 · ok · HTTP 200
Access to a source does not grant permission to reproduce its images.
Die photographHosted in Museum
Samsung Exynos 2600 — Die photograph
Chipwise / NanoPhysics
600 × 509 pxTechnical archive / analysis
Samsung Exynos 2600 SoC. See source caption; no chip layer inferred beyond source evidence
View original die photoRights, provenance & link history
- Rights status
- PERMISSION GRANTED
- Local hosting / thumbnails / hotlinking
- Allowed / Allowed / Not enabled
- Attribution
- Image courtesy of Chipwise · Used with permission
- Identity / confidence
- matched / high
- Evidence reviewed
- 2026-09-09
- Link checked
- 2026-09-09 · ok · HTTP 200
Access to a source does not grant permission to reproduce its images.
Die photographHosted in Museum
Samsung Exynos 2600 — Die photograph
Chipwise / NanoPhysics
600 × 507 pxTechnical archive / analysis
Samsung Exynos 2600 SoC. Frontside die view, as identified by source
View original die photoRights, provenance & link history
- Rights status
- PERMISSION GRANTED
- Local hosting / thumbnails / hotlinking
- Allowed / Allowed / Not enabled
- Attribution
- Image courtesy of Chipwise · Used with permission
- Identity / confidence
- matched / high
- Evidence reviewed
- 2026-09-09
- Link checked
- 2026-09-09 · ok · HTTP 200
Access to a source does not grant permission to reproduce its images.
Source trail
Exynos 2600 ↗ · Samsung
Exynos 2600: Official Introduction | Samsung ↗ · Samsung
Kurnal die catalog: Samsung Exynos 2600 ↗ · Kurnal Insights
Exynos 2600 — product overview and specifications ↗ · Samsung Semiconductor
Galaxy S26 and S26+ — Singapore launch and specifications ↗ · Samsung Newsroom
Exynos 2600 and Exynos 1680: kernel findings ↗ · gamma0burst
Exynos 2600 die-photo block annotations ↗ · Reptalica
Samsung Exynos 2600 SoC — Chipwise image source ↗ · Chipwise / NanoPhysics
Advanced FIB-SEM Cross-Section Analysis of Gate-All-Around devices — Chipwise image source ↗ · Chipwise / NanoPhysics