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A 2 nm GAA mobile SoC with a ten-core C1 CPU, Xclipse 960 graphics, a 32K-MAC NPU and Heat Path Block packaging. Its documented capabilities include LPDDR5X, UFS 4.1, 320 MP imaging and 8K video.
Original analyst catalog value. Public entry gives dimensions but does not document calibration, die boundary convention, specimen provenance or uncertainty.
Original analyst catalog value. Public entry gives dimensions but does not document calibration, die boundary convention, specimen provenance or uncertainty.
Original analyst catalog value. Public entry gives dimensions but does not document calibration, die boundary convention, specimen provenance or uncertainty.
A source-based tour from the C1 CPU tiers to the package, with official capabilities separated from kernel-derived analysis.
VLSI Museum synthesis of the cited sources. · 2026-09-09
Ten cores, three performance tiers
Samsung groups the CPU as one C1-Ultra, three faster C1-Pro cores and six efficiency-oriented C1-Pro cores. The smaller Cortex-A520 class used in Exynos 2500 is replaced by C1-Pro cores. SME2 adds matrix instructions for CPU-side machine learning; it is separate from the dedicated NPU.
The NPU specification is 32K MAC. Samsung also supports ExecuTorch for bringing PyTorch models to its on-device runtime. Virtualization security and hybrid post-quantum cryptography beginning in ROM address isolation and software verification. The MAC figure alone does not establish comparable TOPS.
Xclipse 960 combines ray tracing with ENSS neural upscaling and frame generation. Rendering more frames, reconstructing a higher-resolution image and generating intermediate frames are different workloads, so Samsung’s separate graphics improvement figures should not be combined into one native-rendering speedup.
VPS analyzes scene content and DVNR reduces noise in low-light video. The ISP accepts sensors up to 320 MP, while the documented real-time modes include 108 MP at 30 fps and dual 64 MP + 32 MP input. The media block separately lists 8K30 encoding, 8K60 decoding and APV support.
The Heat Path Block and high-k epoxy molding compound improve the package’s heat-transfer path. This is a package-level design claim: a die photograph does not show the complete stack or the phone’s cooling assembly. Sustained performance also depends on that surrounding system.
Samsung reports up to 39% higher CPU performance, 113% higher generative-AI performance, twice the GPU compute performance and up to 50% better ray tracing versus Exynos 2500. Its other internal-test claims include up to 3× smoother ENSS output, 50% lower ISP power and 16% lower thermal resistance. These are manufacturer test results with workload and environment limitations, not Museum measurements.
gamma0burst reports a 1+3+3+3 CPU grouping and an eight-WGP GPU configuration from Galaxy S26 kernel material. These software descriptions add detail to the official specifications, but do not locate blocks on the die or establish a complete interconnect graph.
Samsung’s Singapore launch table identifies Exynos 2600 in Galaxy S26 and S26+, available from March 11, 2026. Its Bluetooth entries differ between the two phones. Device connectivity, camera sensors and installed memory describe a shipping product configuration; they should not all be attributed to blocks integrated on the application-processor die.
Reading areas and interfaces from a die photograph
Reptalica’s annotations, embedded in Vengineer’s article, estimate CPU, GPU and NPU complex areas. Vengineer highlights the changed placement of the LPDDR PHY regions and asks how they connect through the package. These are useful analysis leads; exact boundaries, calibration and package routing remain unresolved.
Arm describes C1-DSU as managing coherency and memory across C1 CPU clusters, and SI L1 as combining coherent interconnect, a non-coherent NoC and an optional system cache. These documents explain the roles such blocks can play. They do not verify Exynos 2600’s exact NoC, cache capacity, connectivity graph or physical placement.