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Image courtesy of Chipwise · Used with permission. Link the original Chipwise source page and retain its markings and credits. Permission reported by the Museum operator on 2026-09-09. Display resizing and format conversion only; no removal of annotations or watermarks. No onward redistribution or comparison-export licence is granted by the Museum.
SILICON DESIGN / DATE NOT RECORDED
Google Tensor G5 Google’s TSMC 3 nm Pixel 10 SoC, with a faster TPU/CPU and new ISP.
Specifications 7 SOURCE-LINKED FIELDS Identity & fabrication CPU & clock domains AI & security Camera, video & display Connectivity & devices Identity & fabrication Process TSMC 3 nm Manufacturer / primary source Google Scope: silicon-die
CPU & clock domains CPU performance claim 34% faster on average Manufacturer / primary source Google Scope: silicon-die
Google’s comparison with Tensor G4; manufacturer result, not a Museum measurement.
AI & security TPU performance up to 60% more powerful Manufacturer / primary source Google Scope: silicon-die
Google’s comparison with Tensor G4; manufacturer result, not a Museum measurement.
AI first chip to run newest Gemini Nano model Manufacturer / primary source Google Scope: silicon-die
Security new security hardware Manufacturer / primary source Google Scope: silicon-die
Camera, video & display ISP all-new Image Signal Processor Manufacturer / primary source Google Scope: silicon-die
Connectivity & devices Target device Pixel 10 Manufacturer / primary source Google Scope: silicon-die
Suggest a correction Enter the full die exhibit Overview Sources & history Discussion
Record identity & scope silicon design · Google Tensor G5
What this photograph shows Google Tensor G5. Backside/deprocessed die view, as identified by source