GOOGLE / SILICON DESIGN

Google Tensor G5

Google’s TSMC 3 nm Pixel 10 SoC, with a faster TPU/CPU and new ISP.

Image courtesy of Chipwise ·Used with permission

713 × 800 PX SOURCE / 100%

Drag to explore

Image courtesy of Chipwise ·Used with permission· Die photograph · Resized and format-converted for display; original image content and watermarks preserved.

Origin & contributions

Original source · Retrieved 2026-09-09

Chipwise / NanoPhysics · photographer · Included in this image

Image courtesy of Chipwise · Used with permission. Link the original Chipwise source page and retain its markings and credits. Permission reported by the Museum operator on 2026-09-09. Display resizing and format conversion only; no removal of annotations or watermarks. No onward redistribution or comparison-export licence is granted by the Museum.

Google Tensor G5. Backside/deprocessed die view, as identified by source

Source photography; preparation and visible markings are preserved. This photograph supplies no independently verified geometric measurements.

Original & higher resolution

Specifications

7 SOURCE-LINKED FIELDS

Identity & fabrication
Process	Manufacturer / primary sourceGoogle Scope: silicon-die
CPU & clock domains
CPU performance claim	Manufacturer / primary sourceGoogle Scope: silicon-die Google’s comparison with Tensor G4; manufacturer result, not a Museum measurement.
AI & security
TPU performance	Manufacturer / primary sourceGoogle Scope: silicon-die Google’s comparison with Tensor G4; manufacturer result, not a Museum measurement.
AI	Manufacturer / primary sourceGoogle Scope: silicon-die
Security	Manufacturer / primary sourceGoogle Scope: silicon-die
Camera, video & display
ISP	Manufacturer / primary sourceGoogle Scope: silicon-die
Connectivity & devices
Target device	Manufacturer / primary sourceGoogle Scope: silicon-die

Source-linked recordRecord verified 2026-09-09

ARCHITECTURE → RTL → GDS

Design with this record

All design guides ↗

Start with documented specifications, then use the study prompts below. The prompts are engineering guidance, not a claim about this product’s private RTL or physical implementation.

Process: Google ↗

Workload and traffic model

Build a traffic matrix across the documented CPU, graphics, AI and I/O engines. Model concurrent bursts, locality and worst-case response time at shared memory before choosing arbitration or buffering.

Contracts before RTL

Choose a representative producer/consumer path and specify acceptance, ordering, backpressure, outstanding capacity and reset recovery. Turn these contracts into assertions and test scenarios before optimizing the datapath.

A feasible physical plan

Obtain macro abstracts, pin maps, timing libraries and activity-based power estimates. Explore macro proximity, routing channels and power-grid reachability together. An annotated die photograph can suggest study questions, but cannot supply a netlist, PDK or signoff constraints.

Read the record in its physical scope.

Google’s TSMC 3 nm Pixel 10 SoC, with a faster TPU/CPU and new ISP.

This record has identification and source evidence. A deeper architectural article has not yet been written. Visible patterns alone do not establish block functions, capacity or an internal protocol.

THE VISUAL EVIDENCE

Visual sources

2 DOCUMENTED SOURCES

Hosted image provenance · 2

Die photographHosted in Museum

Google Tensor G5 — Die photograph

Chipwise / NanoPhysics

717 × 800 pxTechnical archive / analysis

Google Tensor G5. Frontside die view, as identified by source

View original die photo

Rights, provenance & link history

Rights status: PERMISSION GRANTED
Licence: Used with permission — attribution required ↗
Local hosting / thumbnails / hotlinking: Allowed / Allowed / Not enabled
Attribution: Image courtesy of Chipwise · Used with permission
Identity / confidence: matched / high
Evidence reviewed: 2026-09-09
Link checked: 2026-09-09 · ok · HTTP 200

Reuse evidence ↗

Access to a source does not grant permission to reproduce its images.

Die photographHosted in Museum

Google Tensor G5 — Die photograph

Chipwise / NanoPhysics

713 × 800 pxTechnical archive / analysis

Google Tensor G5. Backside/deprocessed die view, as identified by source

View original die photo

Rights, provenance & link history

Rights status: PERMISSION GRANTED
Licence: Used with permission — attribution required ↗
Local hosting / thumbnails / hotlinking: Allowed / Allowed / Not enabled
Attribution: Image courtesy of Chipwise · Used with permission
Identity / confidence: matched / high
Evidence reviewed: 2026-09-09
Link checked: 2026-09-09 · ok · HTTP 200

Reuse evidence ↗

Access to a source does not grant permission to reproduce its images.

Source trail

5 reasons why Google Tensor G5 is a game-changer for Pixel ↗ · Google

Google Tensor G5 — Chipwise image source ↗ · Chipwise / NanoPhysics