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Collection/Apple/Apple M1 Ultra
VLSI MUSEUM / ENGINEERING RECORD2022
AppleSoC

product family

Visual evidence, at its source.

Explore external photography and documentation alongside the engineering evidence below.

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Apple
PRODUCT FAMILY / 2022

Apple M1 Ultra

Apple desktop SoC announced for Mac Studio, implemented with two M1 Max dies through UltraFusion.

AppleSoC

Research connections

CompanyApple ↗

Specifications

2 SOURCE-LINKED FIELDS
Identity & fabrication
Record year
Manufacturer / primary sourceApple

Scope: M1 Ultra product SoC

Source date: 2022-03-08

Year basis: announced.

Additional specifications
M1 Max dies
Manufacturer / primary sourceApple

Scope: M1 Ultra package

Source date: 2022-03-08

Apple describes the die of two M1 Max chips connected using UltraFusion.

THE VISUAL EVIDENCE

Visual sources

1 DOCUMENTED SOURCES

These additional visual sources open on the publisher’s site.

Chiplet layoutExternal source ↗

Recommended source

M1 Ultra — UltraFusion packaging diagram

Apple

Annotated2022-03-08Primary source

Apple’s labeled packaging illustration shows how two M1 Max dies form M1 Ultra. This is an official explanatory visual, not a physical die photograph.

View original visual source
Rights, provenance & link history
Rights status
UNKNOWN
Licence
No reuse grant established
Local hosting / thumbnails / hotlinking
Not enabled / Not enabled / Not enabled
Attribution
Apple
Identity / confidence
matched / high
Evidence reviewed
2026-09-07
Link checked
2026-09-07 · ok · HTTP 200

Access to a source does not grant permission to reproduce its images.

TECHNICAL ARTICLE

M1 Ultra: two dies treated as one SoC

Apple’s announcement identifies UltraFusion as the packaging path that connects two M1 Max dies to form M1 Ultra.

VLSI Museum synthesis of the cited sources. · 2026-09-07

Scaling at the package boundary

M1 Ultra joins two M1 Max dies. Compute scales across a package boundary, while software sees one chip. A photograph of one constituent die therefore describes only part of the product.

PRIMARY SOURCEApple

The interconnect makes the design possible

Apple specifies a silicon interposer with more than 10,000 signals and 2.5 TB/s of inter-processor bandwidth. Keeping communication close to the dies supports the unified programming model; Apple presents this as an alternative to motherboard-level links.

PRIMARY SOURCEApple

Read the visual at the right scale

The official package illustration is useful for understanding connectivity. It is not an optical die photograph, and it does not establish undocumented physical dimensions or layer construction.

PUBLISHED ANALYSISApple
Follow the documented connections

Follow the connections

2 SOURCE-LINKED RELATIONSHIPS

Record identity & scope

product family · Apple M1 Ultra

M1 Ultra SoC