VLSI KoreaSEMICONDUCTOR REFERENCE
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Find products, devices, processes and manufacturing tools with specifications and original sources.
Specification query syntax
Use cores, threads, clock, boost, l2, l3, tdp, memory or year with =, >=, <=, > or <. Units: GHz, MB, W, GB. Unknown or conflicting values do not match numeric conditions.
Results
cpu
| Compare | Entity | CPU organization | Clock / peak | Cache | Process label | Die area |
|---|---|---|---|---|---|---|
AMD Zen 2 CCDAMD · silicon die · 2019 | 2 CCXsCCXs per CCDphysical core-complex die | unresearched | 16 MBMaximum L3 per CCXphysical core-complex die | unresearched | 74 mm²Die areaOne Zen 2 7nm CPU Core Complex Die (CCD), design-level disclosure | |
Intel 4004Intel · silicon die · 1971 | unresearched | unresearched | unresearched | 10 µmProcess labelprocessor design | unresearched | |
Intel 8086Intel · silicon die · 1978 | unresearched | unresearched | unresearched | 3 µmProcess labelprocessor design | unresearched | |
MOS Technology 6502MOS Technology · silicon die · 1975 | unresearched | unresearched | unresearched | unresearched | unresearched | |
Intel386 DXIntel · product family · 1985 | unresearched | unresearched | unresearched | unresearched | unresearched | |
Intel Pentium 60/66 MHzIntel · silicon die · 1993 | unresearched | unresearched | unresearched | 0.8 µmProcess labeloriginal 60/66 MHz models | unresearched | |
AMD Ryzen 5 3600AMD · product model · 2019 | unresearched | unresearched | 32 MBL3 cachecomplete processor product | unresearched | unresearched | |
AMD Ryzen 5 5600XAMD · product model · 2020 | unresearched | unresearched | 32 MBL3 cachecomplete processor product | unresearched | unresearched |
gpu
| Compare | Entity | Compute organization | Local memory | External memory | Memory bandwidth | Die area |
|---|---|---|---|---|---|---|
NVIDIA GeForce 256NVIDIA · silicon die · 1999 | unresearched | unresearched | unresearched | unresearched | unresearched | |
NVIDIA GH100 full GPU designNVIDIA · silicon die · 2022 | unresearched | unresearched | unresearched | unresearched | 814 mm²Die areaOne full GH100 silicon die powering H100 |
specimen
| Compare | Entity | Subject | Package | Die area |
|---|---|---|---|---|
AMD Zen 3 CCD specimenAMD · physical specimen | unresearched | unresearched | unresearched |
accelerator
| Compare | Entity | Compute organization | Local memory | External memory | Memory bandwidth | Die area |
|---|---|---|---|---|---|---|
NVIDIA A100NVIDIA · silicon die · 2020 | unresearched | unresearched | unresearched | unresearched | 826 mm²Die areaOne GA100 silicon die powering A100 |
Compare specifications
Source values, conditions and entity scope stay together.
| Specification / evidence | Samsung Exynos 2100silicon-die | Samsung Exynos 2600silicon-die |
|---|---|---|
| Record year | official-disclosure · sourcedScope: SoC designSource date: 2021-01-12Year basis: announced. This is distinct from source publication and record update.Source ↗ | Unresearched for this record |
| Process label | official-disclosure · sourcedScope: SoC designSource date: 2021-01-12Source ↗ | Unresearched for this record |
| CPU cores | official-disclosure · sourcedScope: SoC designSource ↗ | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| CPU composition | official-disclosure · sourcedScope: SoC designSource date: 2021-01-12Source ↗ | Unresearched for this record |
| Cortex-X1 clock | official-disclosure · sourcedScope: SoC designSource date: 2021-01-12Source ↗ | Unresearched for this record |
| Announcement date | official-disclosure · sourcedScope: SoC designSamsung announced it through Exynos On 2021.Source ↗ | Unresearched for this record |
| Process | official-disclosure · sourcedScope: SoC designSource ↗ | official-disclosure · sourcedScope: silicon-dieSamsung process designation; not a measured gate dimension.Source ↗ |
| CPU topology | official-disclosure · sourcedScope: SoC designSource ↗ | Unresearched for this record |
| CPU prime core | official-disclosure · sourcedScope: SoC designSource ↗ | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| CPU prime peak | official-disclosure · sourcedScope: SoC designSource ↗ | Unresearched for this record |
| CPU performance cores | official-disclosure · sourcedScope: SoC designSource ↗ | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| CPU efficiency cores | official-disclosure · sourcedScope: SoC designSource ↗ | Unresearched for this record |
| GPU | official-disclosure · sourcedScope: SoC designSource ↗ | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| Graphics apis | official-disclosure · sourcedScope: SoC designSource ↗ | Unresearched for this record |
| NPU architecture | official-disclosure · sourcedScope: SoC designSource ↗ | Unresearched for this record |
| NPU advertised performance | official-disclosure · sourcedScope: SoC designManufacturer-reported performance; workload, precision and test conditions affect comparisons.Source ↗ | Unresearched for this record |
| Memory | official-disclosure · sourcedScope: SoC designSource ↗ | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| Memory bandwidth | official-disclosure · sourcedScope: SoC designSource ↗ | Unresearched for this record |
| Storage | official-disclosure · sourcedScope: SoC designSource ↗ | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| Maximum camera resolution | official-disclosure · sourcedScope: SoC designSource ↗ | official-disclosure · sourcedScope: silicon-dieISP capability; actual phone sensor resolution is device-specific.Source ↗ |
| Camera sensor concurrency | official-disclosure · sourcedScope: SoC designSource ↗ | Unresearched for this record |
| Video encoding | official-disclosure · sourcedScope: SoC designSource ↗ | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| Video decoding | official-disclosure · sourcedScope: SoC designSource ↗ | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| Modem | official-disclosure · sourcedScope: SoC designSource ↗ | Unresearched for this record |
| Modem peak downlink | official-disclosure · sourcedScope: SoC designSource ↗ | Unresearched for this record |
| Production status | official-disclosure · sourcedScope: SoC designSource ↗ | Unresearched for this record |
| Reported die area | third-party-report · sourcedScope: SoC designKurnal’s original die-shot entry reports 10.93 × 11.72 mm and 128.1 mm². Samsung does not publish die area.Source ↗ | third-party-report · sourcedScope: silicon-dieSource date: 2026-05-29Original analyst catalog value. Public entry gives dimensions but does not document calibration, die boundary convention, specimen provenance or uncertainty.Source ↗ |
| Year | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource date: 2025-12-18Year identifies first public introduction where a dated launch is available; see record notes for exceptions.Source ↗ |
| CPU architecture | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| Reported die width | Unresearched for this record | third-party-report · sourcedScope: silicon-dieSource date: 2026-05-29Original analyst catalog value. Public entry gives dimensions but does not document calibration, die boundary convention, specimen provenance or uncertainty.Source ↗ |
| Reported die height | Unresearched for this record | third-party-report · sourcedScope: silicon-dieSource date: 2026-05-29Original analyst catalog value. Public entry gives dimensions but does not document calibration, die boundary convention, specimen provenance or uncertainty.Source ↗ |
| Foundry | Unresearched for this record | third-party-report · sourcedScope: silicon-dieSource date: 2026-05-29Independent analyst attribution.Source ↗ |
| Verified die geometry | Unresearched for this record | unknown · unresearchedScope: silicon-dieSource date: 2025-12-18No source meeting calibrated geometry requirements accepted in this scout pass. Reported measurements, if present, remain separately labeled.Source ↗ |
| CPU configuration | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| CPU efficiency-oriented cores | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| CPU matrix extension | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| GPU features | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| ENSS techniques | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| NPU configuration | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieArray configuration. MAC count is not a TOPS rating without precision, clock and operation-count conventions.Source ↗ |
| AI deployment | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| Display | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| Single-camera processing | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| Dual-camera processing | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| ISP features | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| Video codecs | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieCodec support list; the page does not assign every codec to every listed encode/decode mode.Source ↗ |
| Security | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource ↗ |
| Thermal packaging | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieEMC: epoxy molding compound. Samsung describes high-k EMC in the heat-dissipation context.Source ↗ |
| Product status | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieStatus on the manufacturer page as accessed on 2026-09-09.Source ↗ |
| Documented devices | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource date: 2026-02-26This launch table establishes Singapore variants; other markets can use different processors.Source ↗ |
| Device availability | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource date: 2026-02-26Singapore general availability; distinct from the chip introduction in 2025.Source ↗ |
| Device connectivity | Unresearched for this record | official-disclosure · sourcedScope: silicon-dieSource date: 2026-02-26Device-level specifications, not proof that Wi-Fi or Bluetooth radios are integrated on this SoC.Source ↗ |
| Reported CPU scheduler groups | Unresearched for this record | third-party-report · sourcedScope: silicon-dieSource date: 2026-03-25Kernel-derived report; the two low-frequency C1-Pro groups appear as six cores in the official 1 + 3 + 6 specification.Source ↗ |
| Reported GPU organization | Unresearched for this record | third-party-report · sourcedScope: silicon-dieSource date: 2026-03-25Reported kernel configuration; shader-lane, TMU and ROP counts remain unverified.Source ↗ |
| Reported GPU frequency range | Unresearched for this record | third-party-report · sourcedScope: silicon-dieSource date: 2026-03-25Reported operating table, not guaranteed sustained frequency.Source ↗ |
| Reported NPU organization | Unresearched for this record | third-party-report · sourcedScope: silicon-dieSource date: 2026-03-25Source ↗ |
| Reported modem pairing | Unresearched for this record | third-party-report · sourcedScope: silicon-dieSource date: 2026-03-25The analyst reports an S5410 pairing and no integrated-modem entry in the examined kernel.Source ↗ |
| Estimated CPU complex area | Unresearched for this record | third-party-report · sourcedScope: silicon-dieSource date: 2026-04-25Die-photo annotation; calibration and block-boundary uncertainty are not established. Original post text was accessible through the Vengineer embed.Source ↗ |
| Estimated GPU complex area | Unresearched for this record | third-party-report · sourcedScope: silicon-dieSource date: 2026-04-25Die-photo annotation; calibration and block-boundary uncertainty are not established. Original post text was accessible through the Vengineer embed.Source ↗ |
| Estimated NPU complex area | Unresearched for this record | third-party-report · sourcedScope: silicon-dieSource date: 2026-04-25Die-photo annotation; calibration and block-boundary uncertainty are not established. Original post text was accessible through the Vengineer embed.Source ↗ |
| Estimated SLC + tags area | Unresearched for this record | third-party-report · sourcedScope: silicon-dieSource date: 2026-04-25Die-photo annotation; calibration and block-boundary uncertainty are not established. Original post text was accessible through the Vengineer embed.Source ↗ |
| Reported LPDDR5X PHY regions | Unresearched for this record | third-party-report · sourcedScope: silicon-dieSource date: 2026-04-25An annotated region count does not establish aggregate bus width or package routing.Source ↗ |
Measured benchmarks must include workload/version, configuration, power mode and date. Theoretical peaks and vendor claims are not measured benchmark results.