GD32F103CBT6 logic/SRAM die

ZeptoBars’ March 2016 teardown identifies a GD32F103CBT6 containing a logic/SRAM die and a separate serial-flash die. It reports a 2889 × 3039 µm logic die with 110 pads, nine used for the flash connection. These are observations and analysis of that specimen. They should not silently become a claim that every GD32F103 revision or every related part number uses an identical die pair.

GigaDevice’s current GD32F103CBT6 product entry lists a Cortex-M3 core, 128K bytes of flash, 20K bytes of SRAM, and an LQFP48 package. Those specifications describe the purchasable part’s supported resources. VLSI Museum interpretation: a software-visible SRAM capacity is not necessarily a count of every SRAM bit fabricated inside the package. The specification and a teardown can describe different scopes without one automatically disproving the other.

After etching the logic die, ZeptoBars reports no flash array on it and identifies four large SRAM blocks totalling 128 KiB, interpreted as code storage mirrored from serial flash. That is the teardown author’s explanation of the physical implementation. It is kept separate from GigaDevice’s supported user SRAM specification. Neither a measured startup penalty nor a comparative energy advantage is established by this Museum packet.

Arm’s technical reference manual identifies Cortex-M3 with the Armv7-M profile, 16-bit and 32-bit Thumb instruction encodings, and separate Thread and Handler operating modes. Its Nested Vectored Interrupt Controller cooperates with the core to prioritize exceptions. The documented tail-chaining mechanism reduces redundant work when handling successive interrupts. These are properties of the core architecture; optional debug or memory-protection features still require checking the particular microcontroller implementation.

The GD32F103 family datasheet describes DMA transfers between peripherals and memory, or between memory locations, without the CPU performing each transfer. It also describes GPIO alternate functions and the sharing of pins between peripherals. VLSI Museum interpretation: an MCU is a coordinated system of compute, transfer engines, timers, and interfaces. The design question is often how an event reaches memory and software, not just how quickly the core executes arithmetic.

The datasheet’s device table lists multiple memory sizes and package options across GD32F103. Pin multiplexing means available functions also depend on the exact part and how its pins are assigned. VLSI Museum interpretation: begin a board-level investigation with the CBT6 specification, then use the family manual to understand operation. The die photograph adds physical evidence, but cannot on its own establish which peripheral options are bonded out or guaranteed.