Containing module: Tesla Dojo Training Tile · Assembly photograph, not a die micrograph.
Original source · Retrieved 2026-09-14
Steve Jurvetson · photographer · Included in this image
Credit Steve Jurvetson; link source and CC BY 2.0. Resized and re-encoded by VLSI Museum; no content alteration.
D1 combines programmable processing nodes, distributed SRAM and a mesh network for Tesla’s Dojo training system.
| Identity & fabrication | |
|---|---|
| Record year | Manufacturer / primary sourceTesla Scope: D1 die, not the 25-die training tile Source date: 2021-08-19 Year basis: AI Day 2021 disclosure; specifications from Hot Chips 2022. This is distinct from source publication and record update. |
| Foundry process | Manufacturer / primary sourceTesla / Hot Chips Scope: D1 die, not the 25-die training tile Source date: 2022 |
| Processing nodes | Manufacturer / primary sourceTesla / Hot Chips Scope: D1 die, not the 25-die training tile Source date: 2022 |
| Packaging, power & physical analysis | |
| Die area | Manufacturer / primary sourceTesla / Hot Chips Scope: D1 die, not the 25-die training tile Source date: 2022 |
| Additional specifications | |
| SRAM | Manufacturer / primary sourceTesla / Hot Chips Scope: D1 die, not the 25-die training tile Source date: 2022 |
| BF16 / CFP8 theoretical peak | Manufacturer / primary sourceTesla / Hot Chips Scope: D1 die Conditions: At 2 GHz; vendor theoretical peak; not measured training throughput. Sparsity not specified. Source date: 2022 |
| FP32 theoretical peak | Manufacturer / primary sourceTesla / Hot Chips Scope: D1 die Conditions: At 2 GHz; vendor theoretical peak; not measured training throughput. Source date: 2022 |
| Node SRAM | Manufacturer / primary sourceTesla / Hot Chips Scope: Per processing node Source date: 2022 Software-managed local SRAM; not a conventional cache. |
| Node memory load bandwidth | Manufacturer / primary sourceTesla / Hot Chips Scope: Per processing node Source date: 2022 |
| Node memory store bandwidth | Manufacturer / primary sourceTesla / Hot Chips Scope: Per processing node Source date: 2022 |
| Decode width | Manufacturer / primary sourceEric Quinnell / Tesla AI Hardware Scope: Per processing node Source date: 2022-09-28 |
| Scalar scheduler width | Manufacturer / primary sourceEric Quinnell / Tesla AI Hardware Scope: Per processing node Source date: 2022-09-28 |
| Vector scheduler width | Manufacturer / primary sourceEric Quinnell / Tesla AI Hardware Scope: Per processing node Source date: 2022-09-28 |
| Hardware threads per node | Manufacturer / primary sourceEric Quinnell / Tesla AI Hardware Scope: Per processing node Source date: 2022-09-28 |
| SIMD width | Manufacturer / primary sourceEric Quinnell / Tesla AI Hardware Scope: Per processing node Source date: 2022-09-28 |
We have not yet identified a reliable public visual source for this record. Suggest a die photograph, package image, paper or manufacturer diagram.
TECHNICAL ARTICLE
A programmable node, local SRAM and a distributed network repeat across one die and then across training tiles.
Tesla places 354 nodes and 440 MB of SRAM on a 645 mm² TSMC 7nm die. Twenty-five dies form a training tile; its power delivery and external connectivity belong to the module. The 362 TFLOPS BF16/CFP8 figure is a die-level peak at 2 GHz, not an independently measured training result.
Quinnell’s disclosure shows eight-wide decode feeding four-wide scalar and two-wide vector scheduling. Four hardware threads share resources; a typical application assigns compute and communication threads separately. This organization gives software a way to overlap work and movement without turning each node into a general-purpose, virtual-memory operating-system host.
Chips and Cheese distinguishes the node SRAM from a cache: data is directly addressed, without conventional cache tags or an intervening L1 data cache. Its analysis ties the design to removing tag checks and translation machinery. Those are architectural interpretations, not measurements of application speed; the software still has to place and move useful data.
Nodes connect through a two-dimensional mesh with explicit DMA and synchronization primitives. Longer routes occupy more links, so the disclosed peak arithmetic rate alone cannot predict training throughput. Work placement, remote transfers and barriers must be considered together; a containing-system benchmark would also need its workload and configuration.
5 × 5 D1 chips in the training tile
Tesla / Hot Chips · EvidenceTesla’s Hot Chips disclosure describes the D1 die as containing 354 processing nodes and 440 MB of SRAM in a 645 mm² die. The D1 die is the first integration unit; it is distinct from a training tile composed of multiple D1 dies.
CURATOR INTERPRETATIONDistributed processing makes locality and communication central architectural questions. The disclosed node and SRAM counts help frame those questions but do not supply an independently measured training score.
educational context / reviewed specimen
VLSI Korea