VLSI MUSEUM / ENGINEERING RECORD2026
OpenAIOpenAI custom silicon

silicon design

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SILICON DESIGN / 2026

OpenAI Jalapeño

An OpenAI-designed inference accelerator announced with engineering samples in lab use. Broadcom provides implementation and networking; Celestica contributes system integration.

OpenAIAI accelerator

Research connections

Design owner
Manufacturer / primary sourceOpenAI

Scope: silicon-die

Source date: 2026-06-24

Implementation and networking partner
Manufacturer / primary sourceOpenAI

Scope: silicon-die

Source date: 2026-06-24

Board, rack and system integration
Manufacturer / primary sourceOpenAI

Scope: silicon-die

Source date: 2026-06-24

Disclosed status
Manufacturer / primary sourceOpenAI

Scope: silicon-die

Source date: 2026-06-24

Deployment plan
Manufacturer / primary sourceOpenAI

Scope: silicon-die

Source date: 2026-06-24

Disclosed internal topology
UnconfirmedOpenAI

Scope: silicon-die

Source date: 2026-06-24

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Event photograph (not a die photograph)External source ↗

OpenAI Jalapeño

OpenAI

Primary source

Official event/announcement hero image, not a verified die or package photograph. No image bytes are stored or displayed. Photograph rights and any annotation, crop, measurement or written analysis must be resolved separately.

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Evidence reviewed
2026-09-06
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2026-09-07 · blocked · HTTP 403

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Under the surface.

The announcement describes reducing data movement and balancing compute, memory and networking for language-model inference. It does not disclose the on-chip fabric, memory capacity, process, die area or physical floorplan.

CURATOR INTERPRETATIONThe architectural question is how weights and intermediate state reach compute resources at useful utilization. The published system goal supports this question; it supplies neither a wiring diagram nor reproducible bandwidth measurements. Performance claims remain vendor claims pending a detailed report.