VLSI MUSEUM / ENGINEERING RECORD2021
IBM7 nm

silicon design

The engineering record starts here.

We have not yet identified a reliable public die photograph for this record. Its identity and documented evidence remain open to explore.

SILICON DESIGN / 2021

IBM Telum

IBM’s Telum integrates processor cores and AI inference acceleration for enterprise transactions.

IBMCPU

Research connections

Identity & fabrication
Record year
Manufacturer / primary sourceIBM

Scope: one central-processor die, not the dual-chip module

Source date: 2021-08-23

Year basis: announced. This is distinct from source publication and record update.

Process label
Manufacturer / primary sourceIBM Research

Scope: one central-processor die, not the dual-chip module

Source date: 2022-02-19

The ISSCC abstract explicitly reports 22B per CP die; the 2021 press release uses ambiguous dual-chip-module wording.

CPU & clock domains
CPU cores per die
Manufacturer / primary sourceIBM Research

Scope: one central-processor die, not the dual-chip module

Source date: 2022-02-19

The ISSCC abstract explicitly reports 22B per CP die; the 2021 press release uses ambiguous dual-chip-module wording.

Packaging, power & physical analysis
Transistors per die
Manufacturer / primary sourceIBM Research

Scope: one central-processor die, not the dual-chip module

Source date: 2022-02-19

22 billion is per CP die in the ISSCC abstract. The press release refers to a dual-chip module; do not treat that module count as a per-die claim.

Die area
Manufacturer / primary sourceIBM Research

Scope: One first-generation Telum central-processor die (CP)

Source date: 2022-02-19

Each dual-chip module contains two CP dies. 530 mm² is one die, not the 16-core DCM total.

Help document this silicon.

We have not yet identified a reliable public visual source for this record. Suggest a die photograph, package image, paper or manufacturer diagram.

Under the surface.

The ISSCC abstract identifies eight cores, 22 billion transistors and 530 mm² for one Telum central-processor die. The dual-chip module discussed in the announcement is a different physical object.

CURATOR INTERPRETATIONChoosing the physical boundary changes the meaning of a comparison. A single-die area can be placed on a shared silicon scale; a module-wide count cannot be silently substituted for its per-die count.