MICROARCHITECTURE

Alder Lake

Intel microarchitectures alder lake
Identity & fabrication
Architecture name

Scope: architecture

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

Foundry

Scope: architecture

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

Introduction

Scope: architecture

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

Process

Scope: architecture

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

Architecture core count

Scope: architecture

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

ISA

Scope: architecture

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

Architecture predecessor

Scope: architecture

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

Architecture predecessor

Scope: predecessor 2

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

Architecture predecessor

Scope: predecessor 3

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

Architecture successor

Scope: architecture

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

Architecture successor

Scope: successor 2

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

Cache hierarchy
L1 cache

Scope: core

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

L2 cache

Scope: core

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

L3 cache

Scope: architecture scope

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

Additional specifications
Designer

Scope: architecture

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

Core name

Scope: architecture

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

Core name

Scope: core name 2

Source date: 2022-10-11

Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

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출처와 당시의 맥락

Alder Lake — ChipsWiki, revision 97011

ChipsWiki / WikiChip contributors · third-party-report · source linked