AMD Ryzen 5 1600, marked YD1600BBM6IAE, installed in an AM4 socket. Photographed in 2017; this is the AE specimen, not the later AF revision.

Ilya Plekhanov ·CC BY-SA 4.0· Package photograph · Resized and re-encoded; no content altered.

Origin & contributions

Original source · Retrieved 2026-09-11

Ilya Plekhanov · photographer · Included in this image

Credit Ilya Plekhanov and link source and CC BY-SA 4.0. Resized and re-encoded by VLSI Museum; derivatives remain CC BY-SA 4.0.

SKU / 2017

AMD Ryzen 5 1600

CPU SKU · Ryzen 5 1000

AMDCPUZen+

Research connections

CompanyAMD ↗SeriesRyzen 5 1000 ↗ArchitectureZen ↗Process12 nm ↗PackageµOPGA-1331 ↗

WikiChip archive references

Matched archive addresses are research leads. Capture metadata alone does not verify a specification; field-level evidence is listed below.

amd/ryzen 5/1600 · 2023-01-18 ↗AMD Ryzen 5 1600 · 2025-11-06 ↗

Specifications

62 SOURCE-LINKED FIELDS

Identity & fabrication
Record scope	Published analysisBuildCores community Scope: product-model
Part numbers	Published analysisBuildCores community Scope: product-model
Release year	Published analysisBuildCores community Scope: product-model
Series	Published analysisBuildCores community Scope: product-model
Architecture	Published analysisBuildCores community Scope: product-model
Process	Published analysisBuildCores community Scope: product-model Source process label; mixed chiplet processes and marketing names retained.
Model name	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Foundry	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Model number	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Part number	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Part number	Published analysisChipsWiki / WikiChip contributors Scope: part number 2 Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Part number	Published analysisChipsWiki / WikiChip contributors Scope: part number 3 Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Part number	Published analysisChipsWiki / WikiChip contributors Scope: part number 4 Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Market	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Announcement date	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Release date	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
ISA	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Stepping	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Process technology	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
CPU & clock domains
Core family	Published analysisBuildCores community Scope: product-model
Cores	Published analysisBuildCores community Matching source values (1) 6 · ChipsWiki / WikiChip contributors Amd/ryzen 5/1600 · revision 97010 · {{chip}} / core count · Shared upstream; not independent confirmation. Scope: product-model
Threads	Published analysisBuildCores community Matching source values (1) 12 · ChipsWiki / WikiChip contributors Amd/ryzen 5/1600 · revision 97010 · {{chip}} / thread count · Shared upstream; not independent confirmation. Scope: product-model
Base clock	Published analysisBuildCores community Matching source values (1) 3200 MHz · ChipsWiki / WikiChip contributors Amd/ryzen 5/1600 · revision 97010 · {{chip}} / frequency · Shared upstream; not independent confirmation. Scope: product-model
Boost clock	Published analysisBuildCores community Matching source values (1) 3600 MHz · ChipsWiki / WikiChip contributors Amd/ryzen 5/1600 · revision 97010 · {{chip}} / turbo frequency1 · Shared upstream; not independent confirmation. Scope: product-model
CPU family ID	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
CPU model ID	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
CPU word size	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Cache hierarchy
L2 cache	Published analysisBuildCores community Scope: product-model
L3 cache	Published analysisBuildCores community Scope: product-model
L1 cache	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
L1 instruction cache	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
L1 instruction organization	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
L1 instruction associativity	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
L1 data cache	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
L1 data organization	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
L1 data associativity	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
L2 organization	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
L2 associativity	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
L3 organization	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
L3 associativity	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Memory & interfaces
Memory types	Published analysisBuildCores community Scope: product-model
Memory channels	Published analysisBuildCores community Matching source values (1) 2 · ChipsWiki / WikiChip contributors Amd/ryzen 5/1600 · revision 97010 · {{memory controller}} / channels · Shared upstream; not independent confirmation. Scope: product-model
Maximum memory	Published analysisBuildCores community Scope: product-model
Host interface links	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Host interface rate	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Memory type	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Memory ECC	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Memory controllers	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Memory bandwidth	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Packaging, power & physical analysis
Socket	Published analysisBuildCores community Scope: product-model
Listed TDP	Published analysisBuildCores community Matching source values (1) 65 W · ChipsWiki / WikiChip contributors Amd/ryzen 5/1600 · revision 97010 · {{chip}} / tdp · Shared upstream; not independent confirmation. Scope: product-model Source-listed thermal design rating; not measured workload power.
Product packaging	Published analysisBuildCores community Scope: product-model
Transistors	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Die area	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Package	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-06-08 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Package type	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-06-08 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Package pins	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-06-08 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Additional specifications
Designer	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Product family	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Chipset	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Core name	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.
Maximum CPU sockets	Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-11 Source-reported parameter; source revision 2022-10-11. Not an independent measurement.

THE VISUAL EVIDENCE

Visual sources

1 DOCUMENTED SOURCES

Hosted image provenance · 1

Package photographHosted in Museum

AMD Ryzen 5 1600 — Package photograph

Wikimedia Commons · Ilya Plekhanov

1,920 × 1,440 pxTechnical archive / analysis

AMD Ryzen 5 1600, marked YD1600BBM6IAE, installed in an AM4 socket. Photographed in 2017; this is the AE specimen, not the later AF revision.

Link not yet checked

View original visual source

Rights, provenance & link history

Rights status: CC LICENSED
Licence: CC BY-SA 4.0 ↗
Local hosting / thumbnails / hotlinking: Allowed / Allowed / Not enabled
Attribution: Ilya Plekhanov · CC BY-SA 4.0
Identity / confidence: matched / high
Evidence reviewed: 2026-09-11
Link checked: Not yet checked · unchecked

Reuse evidence ↗

Access to a source does not grant permission to reproduce its images.

Record identity & scope

sku · AMD Ryzen 5 1600

What this photograph shows

AMD Ryzen 5 1600, marked YD1600BBM6IAE, installed in an AM4 socket. Photographed in 2017; this is the AE specimen, not the later AF revision.

YD1600BBAEBOX YD1600BBAFBOX Ryzen 5 1600 Amd ryzen 5 1600