VLSI KoreaExplicit microarch infobox parameter; exact architecture identity match.
ChipsWiki / WikiChip contributors · EvidenceVLSI MUSEUM / ENGINEERING RECORD2018
Cavium16 nm
sku
The engineering record starts here.
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Research connections
WikiChip archive references
Matched archive addresses are research leads. Capture metadata alone does not verify a specification; field-level evidence is listed below.
cavium/thunderx2/cn9960 · 2024-09-11 ↗Specifications
42 SOURCE-LINKED FIELDS| Identity & fabrication | |
|---|---|
| Model name | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Foundry | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Model number | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Part number | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Part number | Published analysisChipsWiki / WikiChip contributors Scope: part number 2 Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Part number | Published analysisChipsWiki / WikiChip contributors Scope: part number 3 Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Part number | Published analysisChipsWiki / WikiChip contributors Scope: part number 4 Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Market | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Announcement date | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Release date | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| ISA | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Architecture | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Process | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Process technology | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| CPU & clock domains | |
| CPU clock — frequency | Published analysisChipsWiki / WikiChip contributors Scope: Multiple clock domains; raw parameter frequency Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| CPU clock — frequency 2 | Published analysisChipsWiki / WikiChip contributors Scope: Multiple clock domains; raw parameter frequency 2 Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| CPU clock — frequency 3 | Published analysisChipsWiki / WikiChip contributors Scope: Multiple clock domains; raw parameter frequency 3 Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| CPU clock — frequency 4 | Published analysisChipsWiki / WikiChip contributors Scope: Multiple clock domains; raw parameter frequency 4 Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| CPU word size | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Cores | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Threads | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Cache hierarchy | |
| L1 cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| L1 instruction cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| L1 instruction organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| L1 instruction associativity | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| L1 data cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| L1 data organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| L1 data associativity | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| L2 cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| L2 organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| L2 associativity | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| L3 cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| L3 organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Memory & interfaces | |
| Maximum memory | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Memory type | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Memory ECC | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Memory controllers | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Memory channels | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Memory bandwidth | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Additional specifications | |
| Designer | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Product family | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
| Maximum CPU sockets | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-12-04 Source-reported parameter; source revision 2018-12-04. Not an independent measurement. |
THE VISUAL EVIDENCE
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1 SOURCE-LINKED RELATIONSHIPSRecord identity & scope
sku · ThunderX2 CN9960