VLSI Koreasku
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We have not yet identified a reliable public die photograph for this record. Its identity and documented evidence remain open to explore.
Research connections
WikiChip archive references
Matched archive addresses are research leads. Capture metadata alone does not verify a specification; field-level evidence is listed below.
cavium/octeon tx/cn8020 · 2022-09-25 ↗Specifications
24 SOURCE-LINKED FIELDS| Identity & fabrication | |
|---|---|
| Model name | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| Market | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| Series | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| ISA | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| Architecture | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| Process technology | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| CPU & clock domains | |
| Base clock | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| CPU word size | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| Cores | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| Threads | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| Cache hierarchy | |
| L1 cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| L1 instruction cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| L1 instruction organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| L1 data cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| L1 data organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| L2 cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| L2 organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| Memory & interfaces | |
| Maximum memory | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| Memory type | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| Memory ECC | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| Memory controllers | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| Additional specifications | |
| Designer | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| Product family | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
| Maximum CPU sockets | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2019-02-02 Source-reported parameter; source revision 2019-02-02. Not an independent measurement. |
Visual sources
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Record identity & scope
sku · CN8020