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ChipsWiki / WikiChip contributors · Evidencesku
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WikiChip archive references
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cavium/octeon/cn3110-400bg868-exp · 2023-12-03 ↗Specifications
46 SOURCE-LINKED FIELDS| Identity & fabrication | |
|---|---|
| Model name | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Foundry | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Model number | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Part number | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Market | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Announcement date | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Release date | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Series | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| ISA | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Architecture | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Process | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Process technology | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| CPU & clock domains | |
| Base clock | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| CPU word size | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Cores | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Threads | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Cache hierarchy | |
| L1 cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| L1 instruction cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| L1 instruction organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| L1 instruction associativity | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| L1 data cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| L1 data organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| L1 data associativity | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| L2 cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| L2 organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| L2 associativity | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Memory & interfaces | |
| Maximum memory | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Memory type — Cache (section 1) | Published analysisChipsWiki / WikiChip contributors Scope: Cache (section 1) Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Memory ECC — Cache (section 1) | Published analysisChipsWiki / WikiChip contributors Scope: Cache (section 1) Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Maximum memory — Cache (section 1) | Published analysisChipsWiki / WikiChip contributors Scope: Cache (section 1) Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Memory controllers — Cache (section 1) | Published analysisChipsWiki / WikiChip contributors Scope: Cache (section 1) Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Memory channels — Cache (section 1) | Published analysisChipsWiki / WikiChip contributors Scope: Cache (section 1) Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Memory bandwidth — Cache (section 1) | Published analysisChipsWiki / WikiChip contributors Scope: Cache (section 1) Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Memory type — Memory controller (section 2) | Published analysisChipsWiki / WikiChip contributors Scope: Memory controller (section 2) Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Memory ECC — Memory controller (section 2) | Published analysisChipsWiki / WikiChip contributors Scope: Memory controller (section 2) Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Maximum memory — Memory controller (section 2) | Published analysisChipsWiki / WikiChip contributors Scope: Memory controller (section 2) Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Memory controllers — Memory controller (section 2) | Published analysisChipsWiki / WikiChip contributors Scope: Memory controller (section 2) Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Memory channels — Memory controller (section 2) | Published analysisChipsWiki / WikiChip contributors Scope: Memory controller (section 2) Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Memory bandwidth — Memory controller (section 2) | Published analysisChipsWiki / WikiChip contributors Scope: Memory controller (section 2) Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Packaging, power & physical analysis | |
| Package | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-06-23 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Package type | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-06-23 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Package pins | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-06-23 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Additional specifications | |
| Designer | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Product family | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Core name | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
| Maximum CPU sockets | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2017-12-13 Source-reported parameter; source revision 2017-12-13. Not an independent measurement. |
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1 SOURCE-LINKED RELATIONSHIPSRecord identity & scope
sku · CN3110-400 EXP