VLSI Koreasku
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We have not yet identified a reliable public die photograph for this record. Its identity and documented evidence remain open to explore.
Research connections
WikiChip archive references
Matched archive addresses are research leads. Capture metadata alone does not verify a specification; field-level evidence is listed below.
pezy/pezy-1 · 2022-09-28 ↗Specifications
27 SOURCE-LINKED FIELDS| Identity & fabrication | |
|---|---|
| Model name | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Foundry | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Model number | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Market | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Announcement date | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Release date | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Process | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Process technology | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| CPU & clock domains | |
| Base clock | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Cores | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Cache hierarchy | |
| L1 cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| L1 instruction cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| L1 instruction organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| L1 data cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| L1 data organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| L2 cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| L2 organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Memory & interfaces | |
| Memory type | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Memory ECC | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Memory controllers | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Memory channels | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Memory bandwidth | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Packaging, power & physical analysis | |
| Die area | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Package | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Package type | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Socket | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
| Additional specifications | |
| Designer | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2018-10-20 Source-reported parameter; source revision 2018-10-20. Not an independent measurement. |
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Record identity & scope
sku · PEZY-1