VLSI KoreaExplicit microarch infobox parameter; exact architecture identity match.
ChipsWiki / WikiChip contributors · EvidenceVLSI MUSEUM / ENGINEERING RECORD2020
Intel14 nm
sku
The engineering record starts here.
We have not yet identified a reliable public die photograph for this record. Its identity and documented evidence remain open to explore.
Research connections
Specifications
47 SOURCE-LINKED FIELDS| Identity & fabrication | |
|---|---|
| Model name | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Foundry | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Model number | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Market | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Announcement date | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Release date | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Series | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| ISA | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Architecture | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Process | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Process technology | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| CPU & clock domains | |
| Base clock | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Boost clock | Published analysisChipsWiki / WikiChip contributors Scope: one active core Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| CPU family ID | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| CPU word size | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Cores | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Threads | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Cache hierarchy | |
| L1 cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| L1 instruction cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| L1 instruction organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| L1 instruction associativity | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| L1 data cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| L1 data organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| L1 data associativity | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| L2 cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| L2 organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| L2 associativity | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| L3 cache | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| L3 organization | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| L3 associativity | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Memory & interfaces | |
| Host interface | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Host interface links | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Host interface rate | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Maximum memory | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Memory type | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Memory ECC | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Memory controllers | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Memory channels | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Memory bandwidth | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Packaging, power & physical analysis | |
| Listed TDP | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Additional specifications | |
| Designer | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| S-spec | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Product family | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Platform | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Chipset | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Core name | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
| Maximum CPU sockets | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-08-03 Source-reported parameter; source revision 2022-08-03. Not an independent measurement. |
THE VISUAL EVIDENCE
0 DOCUMENTED SOURCESVisual sources
Help document this silicon.
We have not yet identified a reliable public visual source for this record. Suggest a die photograph, package image, paper or manufacturer diagram.
Follow the connections
1 SOURCE-LINKED RELATIONSHIPSRecord identity & scope
sku · Xeon Silver 4215R