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칩의 기록은 여기서 시작합니다.
이 기록의 신뢰할 수 있는 공개 다이 사진은 아직 확인하지 못했습니다. 신원과 확인된 기술 근거는 계속 탐색할 수 있습니다.
관련 기술 탐색
WikiChip 보관 자료
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intel/core i5/i5-13600kf · 2024-02-22 ↗사양
72 SOURCE-LINKED FIELDS| Identity & fabrication | |
|---|---|
| Record scope | Published analysisBuildCores community Scope: product-model |
| Part numbers | Published analysisBuildCores community Scope: product-model |
| Release year | Published analysisBuildCores community Scope: product-model |
| Series | Published analysisBuildCores community Scope: product-model |
| Architecture | Published analysisBuildCores community Matching source values (1)Raptor Lake · ChipsWiki / WikiChip contributors Scope: product-model |
| Process | Published analysisBuildCores community Matching source values (1)Intel 7 · ChipsWiki / WikiChip contributors Scope: product-model Source process label; mixed chiplet processes and marketing names retained. |
| Model name | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Foundry | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Model number | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Part number | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Part number | Published analysisChipsWiki / WikiChip contributors Scope: part number 2 Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Market | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Announcement date | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Release date | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| ISA | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Stepping | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Process technology | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| CPU & clock domains | |
| Core family | Published analysisBuildCores community Scope: product-model |
| Cores | Published analysisBuildCores community Matching source values (1)14 · ChipsWiki / WikiChip contributors Scope: product-model |
| Threads | Published analysisBuildCores community Matching source values (1)20 · ChipsWiki / WikiChip contributors Scope: product-model |
| Performance cores | Published analysisBuildCores community Scope: product-model |
| Efficiency cores | Published analysisBuildCores community Scope: product-model |
| Base clock | Published analysisBuildCores community Scope: product-model |
| Boost clock | Published analysisBuildCores community Matching source values (1)5100 MHz · ChipsWiki / WikiChip contributors Scope: product-model |
| Efficiency-core Base clock | Published analysisBuildCores community Scope: product-model |
| Efficiency-core Boost clock | Published analysisBuildCores community Scope: product-model |
| CPU clock — frequency | Published analysisChipsWiki / WikiChip contributors Scope: Multiple clock domains; raw parameter frequency Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| CPU clock — frequency 2 | Published analysisChipsWiki / WikiChip contributors Scope: Multiple clock domains; raw parameter frequency 2 Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| CPU family ID | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| CPU model ID | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| CPU word size | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Cache hierarchy | |
| L2 cache | Published analysisBuildCores community Scope: product-model |
| L3 cache | Published analysisBuildCores community Scope: product-model |
| L1 cache — Cache / Small Core (section 1) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Small Core (section 1) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L1 instruction cache — Cache / Small Core (section 1) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Small Core (section 1) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L1 instruction organization — Cache / Small Core (section 1) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Small Core (section 1) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L1 data cache — Cache / Small Core (section 1) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Small Core (section 1) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L1 data organization — Cache / Small Core (section 1) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Small Core (section 1) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L2 cache — Cache / Small Core (section 1) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Small Core (section 1) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L2 organization — Cache / Small Core (section 1) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Small Core (section 1) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L3 cache — Cache / Small Core (section 1) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Small Core (section 1) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L3 organization — Cache / Small Core (section 1) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Small Core (section 1) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L1 cache — Cache / Big Core (section 2) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Big Core (section 2) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L1 instruction cache — Cache / Big Core (section 2) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Big Core (section 2) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L1 instruction organization — Cache / Big Core (section 2) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Big Core (section 2) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L1 data cache — Cache / Big Core (section 2) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Big Core (section 2) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L1 data organization — Cache / Big Core (section 2) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Big Core (section 2) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L2 cache — Cache / Big Core (section 2) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Big Core (section 2) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L2 organization — Cache / Big Core (section 2) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Big Core (section 2) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L3 cache — Cache / Big Core (section 2) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Big Core (section 2) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| L3 organization — Cache / Big Core (section 2) | Published analysisChipsWiki / WikiChip contributors Scope: Cache / Big Core (section 2) Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Memory & interfaces | |
| Memory types | Published analysisBuildCores community Scope: product-model |
| Memory channels | Published analysisBuildCores community Matching source values (1)2 · ChipsWiki / WikiChip contributors Scope: product-model |
| Maximum memory | Published analysisBuildCores community Scope: product-model |
| Host interface | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Host interface links | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Host interface rate | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Memory type | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Memory type | Published analysisChipsWiki / WikiChip contributors Scope: type 2 Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Memory ECC | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Memory controllers | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Memory bandwidth | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Packaging, power & physical analysis | |
| Socket | Published analysisBuildCores community Scope: product-model |
| Listed TDP | Published analysisBuildCores community Matching source values (1)125 W · ChipsWiki / WikiChip contributors Scope: product-model Source-listed thermal design rating; not measured workload power. |
| Listed PPT | Published analysisBuildCores community Scope: product-model |
| Product packaging | Published analysisBuildCores community Scope: product-model |
| Additional specifications | |
| Designer | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| S-spec | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Product family | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Chipset | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Core name | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
| Maximum CPU sockets | Published analysisChipsWiki / WikiChip contributors Scope: product-model Source date: 2022-10-03 Source-reported parameter; source revision 2022-10-03. Not an independent measurement. |
시각 자료
이 칩의 근거를 더해 주세요.
이 기록의 신뢰할 수 있는 공개 시각 자료는 아직 확인하지 못했습니다. 다이 사진·패키지 이미지·논문·제조사 도해를 제안할 수 있습니다.
기록의 신원과 범위
sku · Intel Core i5 13600KF