AMD / SPECIMEN

AMD Radeon VII · Vega20

Polysilicon / lower-layer view of AMD Radeon VII · Vega20, photographed by FritzchensFritz. Identification follows the linked photographer's caption. This is a documented photographic specimen, not a claim that every product with this name uses identical silicon. The original page contains the preparation, microscopy and capture details.

AMD Radeon VII · Vega20 DIE PHOTOGRAPH

AMD Radeon VII · Vega20 — Polysilicon / lower-layer view

1280 × 810 PX SOURCE / 100%

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FritzchensFritz ·CC0· Die photograph · Commons 1280-pixel photographic derivative retained; additional responsive AVIF/WebP encodings. No crop, recoloring, generative edits or added watermark.

Origin & contributions

Original source · Retrieved not recorded

FritzchensFritz · photographer · Included in this image

Attribution and license link retained for every photograph; separate per-file source metadata and acquisition hashes preserved.

Photographed specimen identified by its creator as AMD Radeon VII · Vega20. Polysilicon / lower-layer view. This image is not assigned to other SKUs or used to infer die dimensions.

Original & higher resolution

Specifications

3 SOURCE-LINKED FIELDS

Identity & fabrication
Process label	Published analysisWikimedia Commons · FritzchensFritz Scope: physical-specimen Photographer-supplied label, not an independently verified foundry disclosure.
Additional specifications
Photographed specimen	Published analysisWikimedia Commons · FritzchensFritz Scope: physical-specimen
Photographic view	Published analysisWikimedia Commons · FritzchensFritz Scope: physical-specimen

Source-linked record

ARCHITECTURE → RTL → GDS

Design with this record

All design guides ↗

Start with documented specifications, then use the study prompts below. The prompts are engineering guidance, not a claim about this product’s private RTL or physical implementation.

Process label: Wikimedia Commons · FritzchensFritz ↗

Workload and traffic model

Fix precision and workload shape before comparing compute rates. Track external-memory bytes, shared-memory reuse and occupancy separately; a peak arithmetic rate is only one bound on useful throughput.

Contracts before RTL

Choose a representative producer/consumer path and specify acceptance, ordering, backpressure, outstanding capacity and reset recovery. Turn these contracts into assertions and test scenarios before optimizing the datapath.

A feasible physical plan

Obtain macro abstracts, pin maps, timing libraries and activity-based power estimates. Explore macro proximity, routing channels and power-grid reachability together. An annotated die photograph can suggest study questions, but cannot supply a netlist, PDK or signoff constraints.

Read the record in its physical scope.

This record has identification and source evidence. A deeper architectural article has not yet been written. Visible patterns alone do not establish block functions, capacity or an internal protocol.

THE VISUAL EVIDENCE

Visual sources

1 DOCUMENTED SOURCES

Hosted image provenance · 1

Die photographHosted in Museum

AMD Radeon VII · Vega20 — Die photograph

Wikimedia Commons · FritzchensFritz

7,162 × 4,532 pxTechnical archive / analysis

Photographed specimen identified by its creator as AMD Radeon VII · Vega20. Polysilicon / lower-layer view. This image is not assigned to other SKUs or used to infer die dimensions.

Link not yet checked

View original die photo

Rights, provenance & link history

Rights status: PUBLIC DOMAIN
Licence: CC0 ↗
Local hosting / thumbnails / hotlinking: Allowed / Allowed / Not enabled
Attribution: FritzchensFritz / CC0 / Wikimedia Commons
Identity / confidence: matched / high
Evidence reviewed: 2026-09-06
Link checked: Not yet checked · unchecked

Reuse evidence ↗

Access to a source does not grant permission to reproduce its images.

Source trail

AMD@7nm@GCN 5th gen@Vega20@Radeon VII@ - @ DSCx2 polysilicon layer@IR Makro.jpg ↗ · Wikimedia Commons · FritzchensFritz