VLSI Korea
Workload and traffic model
Build a traffic matrix across the documented CPU, graphics, AI and I/O engines. Model concurrent bursts, locality and worst-case response time at shared memory before choosing arbitration or buffering.
BROADCOM / SILICON DESIGN
Broadcom BCM2712 — D0 stepping
Raspberry Pi 5 application processor; fields apply regardless of D0 stepping.
Broadcom BCM2712 — D0 stepping DIE PHOTOGRAPH
Image courtesy of Chipwise ·Used with permission· Die photograph · Resized and format-converted for display; original image content and watermarks preserved.
Origin & contributions
Original source · Retrieved 2026-09-09
Chipwise / NanoPhysics · photographer · Included in this image
Image courtesy of Chipwise · Used with permission. Link the original Chipwise source page and retain its markings and credits. Permission reported by the Museum operator on 2026-09-09. Display resizing and format conversion only; no removal of annotations or watermarks. No onward redistribution or comparison-export licence is granted by the Museum.
BCM2712 Technology Analysis Report. See source caption; no chip layer inferred beyond source evidence
Source photography; preparation and visible markings are preserved. This photograph supplies no independently verified geometric measurements.
Specifications
9 SOURCE-LINKED FIELDS| CPU & clock domains | |
|---|---|
| CPU | Manufacturer / primary sourceRaspberry Pi Scope: silicon-die Raspberry Pi 5 platform specification; this source does not establish a difference between BCM2712 silicon revisions. |
| CPU clock | Manufacturer / primary sourceRaspberry Pi Scope: silicon-die Raspberry Pi 5 platform specification; this source does not establish a difference between BCM2712 silicon revisions. |
| CPU cache | Manufacturer / primary sourceRaspberry Pi Scope: silicon-die Raspberry Pi 5 platform specification; this source does not establish a difference between BCM2712 silicon revisions. |
| Graphics | |
| GPU | Manufacturer / primary sourceRaspberry Pi Scope: silicon-die Raspberry Pi 5 platform specification; this source does not establish a difference between BCM2712 silicon revisions. |
| Graphics APIs | Manufacturer / primary sourceRaspberry Pi Scope: silicon-die Raspberry Pi 5 platform specification; this source does not establish a difference between BCM2712 silicon revisions. |
| Memory & interfaces | |
| Memory | Manufacturer / primary sourceRaspberry Pi Scope: silicon-die Raspberry Pi 5 platform specification; this source does not establish a difference between BCM2712 silicon revisions. |
| PCIe | Manufacturer / primary sourceRaspberry Pi Scope: silicon-die Raspberry Pi 5 platform specification; this source does not establish a difference between BCM2712 silicon revisions. |
| Camera, video & display | |
| Display output | Manufacturer / primary sourceRaspberry Pi Scope: silicon-die Raspberry Pi 5 platform specification; this source does not establish a difference between BCM2712 silicon revisions. |
| Video decode | Manufacturer / primary sourceRaspberry Pi Scope: silicon-die Raspberry Pi 5 platform specification; this source does not establish a difference between BCM2712 silicon revisions. |
Source-linked recordRecord verified
ARCHITECTURE → RTL → GDS
All design guides ↗Design with this record
Start with documented specifications, then use the study prompts below. The prompts are engineering guidance, not a claim about this product’s private RTL or physical implementation.
- Memory
- Raspberry Pi ↗
Contracts before RTL
Choose a representative producer/consumer path and specify acceptance, ordering, backpressure, outstanding capacity and reset recovery. Turn these contracts into assertions and test scenarios before optimizing the datapath.
A feasible physical plan
Obtain macro abstracts, pin maps, timing libraries and activity-based power estimates. Explore macro proximity, routing channels and power-grid reachability together. An annotated die photograph can suggest study questions, but cannot supply a netlist, PDK or signoff constraints.
Read the record in its physical scope.
Raspberry Pi 5 application processor; fields apply regardless of D0 stepping.
This record has identification and source evidence. A deeper architectural article has not yet been written. Visible patterns alone do not establish block functions, capacity or an internal protocol.
Follow the connections
1 SOURCE-LINKED RELATIONSHIPSComparison image contains multiple dies; it is not a photograph of one die or a geometric measurement.
Chipwise / NanoPhysics · EvidenceTHE VISUAL EVIDENCE
2 DOCUMENTED SOURCESVisual sources
Hosted image provenance · 2
Die photographHosted in Museum
Broadcom BCM2712 — D0 stepping — Die photograph
Chipwise / NanoPhysics
1,878 × 1,920 pxTechnical archive / analysis
BCM2712 Technology Analysis Report. Frontside die view, as identified by source
View original die photoRights, provenance & link history
- Rights status
- PERMISSION GRANTED
- Local hosting / thumbnails / hotlinking
- Allowed / Allowed / Not enabled
- Attribution
- Image courtesy of Chipwise · Used with permission
- Identity / confidence
- matched / high
- Evidence reviewed
- 2026-09-09
- Link checked
- 2026-09-09 · ok · HTTP 200
Access to a source does not grant permission to reproduce its images.
Die photographHosted in Museum
Broadcom BCM2712 — D0 stepping — Die photograph
Chipwise / NanoPhysics
1,878 × 1,920 pxTechnical archive / analysis
BCM2712 Technology Analysis Report. See source caption; no chip layer inferred beyond source evidence
View original die photoRights, provenance & link history
- Rights status
- PERMISSION GRANTED
- Local hosting / thumbnails / hotlinking
- Allowed / Allowed / Not enabled
- Attribution
- Image courtesy of Chipwise · Used with permission
- Identity / confidence
- matched / high
- Evidence reviewed
- 2026-09-09
- Link checked
- 2026-09-09 · ok · HTTP 200
Access to a source does not grant permission to reproduce its images.
Source trail
Raspberry Pi 5 product brief ↗ · Raspberry Pi
BCM2712 Technology Analysis Report — Chipwise image source ↗ · Chipwise / NanoPhysics