APPLE / SILICON DESIGN

Apple A18

Second-generation 3 nm iPhone SoC with a six-core CPU and five-core GPU.

Apple A18 DIE PHOTOGRAPH
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Image courtesy of Chipwise ·Used with permission· Die photograph · Resized and format-converted for display; original image content and watermarks preserved.
Origin & contributions

Original source · Retrieved 2026-09-09

Chipwise / NanoPhysics · photographer · Included in this image

Image courtesy of Chipwise · Used with permission. Link the original Chipwise source page and retain its markings and credits. Permission reported by the Museum operator on 2026-09-09. Display resizing and format conversion only; no removal of annotations or watermarks. No onward redistribution or comparison-export licence is granted by the Museum.

Apple A18 & A18 pro die shot. See source caption; no chip layer inferred beyond source evidence

Source photography; preparation and visible markings are preserved. This photograph supplies no independently verified geometric measurements.

Original & higher resolution
Identity & fabrication
Year
Manufacturer / primary sourceApple

Scope: silicon-die

Source date: 2024-09-09

Year identifies first public introduction where a dated launch is available; see record notes for exceptions.

Process
Manufacturer / primary sourceApple

Scope: silicon-die

Foundry
Published analysisKurnal Insights

Scope: silicon-die

Source date: 2026-05-05

Independent analyst attribution.

CPU & clock domains
CPU
Manufacturer / primary sourceApple

Scope: silicon-die

Graphics
GPU
Manufacturer / primary sourceApple

Scope: silicon-die

Ray tracing
Manufacturer / primary sourceApple

Scope: silicon-die

AI & security
Neural Engine cores
Manufacturer / primary sourceApple

Scope: silicon-die

Source date: 2024-09-09

Neural Engine
Manufacturer / primary sourceApple

Scope: silicon-die

Packaging, power & physical analysis
Reported die width
Published analysisKurnal Insights

Scope: silicon-die

Source date: 2026-05-05

Original analyst catalog value. Public entry gives dimensions but does not document calibration, die boundary convention, specimen provenance or uncertainty.

Reported die height
Published analysisKurnal Insights

Scope: silicon-die

Source date: 2026-05-05

Original analyst catalog value. Public entry gives dimensions but does not document calibration, die boundary convention, specimen provenance or uncertainty.

Reported die area
Published analysisKurnal Insights

Scope: silicon-die

Source date: 2026-05-05

Original analyst catalog value. Public entry gives dimensions but does not document calibration, die boundary convention, specimen provenance or uncertainty.

Verified die geometry
UnconfirmedApple

Scope: silicon-die

Source date: 2024-09-09

No source meeting calibrated geometry requirements accepted in this scout pass. Reported measurements, if present, remain separately labeled.

Source-linked recordEditorial update

Start with documented specifications, then use the study prompts below. The prompts are engineering guidance, not a claim about this product’s private RTL or physical implementation.

GPU
Apple ↗
Process
Apple ↗
Reported die area
Kurnal Insights ↗
01

Workload and traffic model

Build a traffic matrix across the documented CPU, graphics, AI and I/O engines. Model concurrent bursts, locality and worst-case response time at shared memory before choosing arbitration or buffering.

02

Contracts before RTL

Choose a representative producer/consumer path and specify acceptance, ordering, backpressure, outstanding capacity and reset recovery. Turn these contracts into assertions and test scenarios before optimizing the datapath.

03

A feasible physical plan

Obtain macro abstracts, pin maps, timing libraries and activity-based power estimates. Explore macro proximity, routing channels and power-grid reachability together. An annotated die photograph can suggest study questions, but cannot supply a netlist, PDK or signoff constraints.

Read the record in its physical scope.

Second-generation 3 nm iPhone SoC with a six-core CPU and five-core GPU.

This record has identification and source evidence. A deeper architectural article has not yet been written. Visible patterns alone do not establish block functions, capacity or an internal protocol.

Hosted image provenance · 2
Die photographHosted in Museum

Apple A18 — Die photograph

Chipwise / NanoPhysics

600 × 399 pxTechnical archive / analysis

Apple A18 & A18 pro die shot. Frontside die view, as identified by source

View original die photo
Rights, provenance & link history
Rights status
PERMISSION GRANTED
Local hosting / thumbnails / hotlinking
Allowed / Allowed / Not enabled
Attribution
Image courtesy of Chipwise · Used with permission
Identity / confidence
matched / high
Evidence reviewed
2026-09-09
Link checked
2026-09-09 · ok · HTTP 200
Reuse evidence ↗

Access to a source does not grant permission to reproduce its images.

Die photographHosted in Museum

Apple A18 — Die photograph

Chipwise / NanoPhysics

600 × 400 pxTechnical archive / analysis

Apple A18 & A18 pro die shot. See source caption; no chip layer inferred beyond source evidence

View original die photo
Rights, provenance & link history
Rights status
PERMISSION GRANTED
Local hosting / thumbnails / hotlinking
Allowed / Allowed / Not enabled
Attribution
Image courtesy of Chipwise · Used with permission
Identity / confidence
matched / high
Evidence reviewed
2026-09-09
Link checked
2026-09-09 · ok · HTTP 200
Reuse evidence ↗

Access to a source does not grant permission to reproduce its images.

Source trail

Apple introduces iPhone 16 and iPhone 16 Plus ↗ · Apple

Kurnal die catalog: Apple A18 ↗ · Kurnal Insights

Apple introduces iPhone 16 and iPhone 16 Plus ↗ · Apple

Apple A18 & A18 pro die shot — Chipwise image source ↗ · Chipwise / NanoPhysics