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The JDC page is a hosted launch summary, not a processor launch release.","entityId":"hisilicon-kirin-9030","scope":"product-model","sourceUrl":"https://jdc.huawei.com/jdc/refactor/viewthread?tid=1159979","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"},{"key":"Documented device","value":"Mate 80 Pro, 12 GB RAM","sourceId":"huawei-mate80pro-specs","location":"处理器 / Processor","evidenceClass":"official-disclosure","entityId":"hisilicon-kirin-9030","scope":"product-model","sourceUrl":"https://consumer.huawei.com/cn/phones/mate80-pro/specs/","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"},{"key":"Process","value":"SMIC N+3","sourceId":"semianalysis-kirin9030-process","location":"Architecture & PPA","evidenceClass":"independent-measurement","entityId":"hisilicon-kirin-9030","scope":"product-model","sourceUrl":"https://newsletter.semianalysis.com/p/steel-smic-n3-teardown","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"},{"key":"Foundry","value":"SMIC","sourceId":"semianalysis-kirin9030-process","location":"Architecture & PPA","evidenceClass":"independent-measurement","entityId":"hisilicon-kirin-9030","scope":"product-model","sourceUrl":"https://newsletter.semianalysis.com/p/steel-smic-n3-teardown","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"},{"key":"Reported die width","value":12.95,"sourceId":"kurnal-hisilicon-kirin-9030","location":"Dimensions / Area","evidenceClass":"third-party-report","unit":"mm","note":"Original analyst catalog value. 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Public entry gives dimensions but does not document calibration, die boundary convention, specimen provenance or uncertainty.","entityId":"hisilicon-kirin-9030","scope":"product-model","sourceUrl":"https://kurnal-insights.com/en/dieshot/hisilicon-hi36d0-kirin-9030/","sourceDate":"2026-07-28","retrievedAt":"2026-09-06","researchState":"sourced"},{"key":"Reported die area","value":141.67,"sourceId":"kurnal-hisilicon-kirin-9030","location":"Dimensions / Area","evidenceClass":"third-party-report","unit":"mm²","note":"Original analyst catalog value. Public entry gives dimensions but does not document calibration, die boundary convention, specimen provenance or uncertainty.","entityId":"hisilicon-kirin-9030","scope":"product-model","sourceUrl":"https://kurnal-insights.com/en/dieshot/hisilicon-hi36d0-kirin-9030/","sourceDate":"2026-07-28","retrievedAt":"2026-09-06","researchState":"sourced"},{"key":"Verified die geometry","value":null,"sourceId":"huawei-mate80pro-specs","location":"Evidence review","evidenceClass":"unknown","note":"No source meeting calibrated geometry requirements accepted in this scout pass. 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The JDC page is a hosted launch summary, not a processor launch release.","entityId":"hisilicon-kirin-9030-pro","scope":"product-model","sourceUrl":"https://jdc.huawei.com/jdc/refactor/viewthread?tid=1159979","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"},{"key":"Documented device","value":"Mate 80 Pro Max","sourceId":"huawei-mate80promax-specs","location":"处理器 / Processor","evidenceClass":"official-disclosure","entityId":"hisilicon-kirin-9030-pro","scope":"product-model","sourceUrl":"https://consumer.huawei.com/cn/phones/mate80-pro-max/specs/","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"},{"key":"Additional device","value":"Mate 80 Pro, 16 GB RAM","sourceId":"huawei-mate80pro-specs","location":"处理器 / Processor","evidenceClass":"official-disclosure","entityId":"hisilicon-kirin-9030-pro","scope":"product-model","sourceUrl":"https://consumer.huawei.com/cn/phones/mate80-pro/specs/","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"},{"key":"Process","value":"SMIC N+3","sourceId":"semianalysis-kirin9030-process","location":"Kirin 9030 Pro physical analysis","evidenceClass":"independent-measurement","entityId":"hisilicon-kirin-9030-pro","scope":"product-model","sourceUrl":"https://newsletter.semianalysis.com/p/steel-smic-n3-teardown","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"},{"key":"Foundry","value":"SMIC","sourceId":"semianalysis-kirin9030-process","location":"Physical analysis","evidenceClass":"independent-measurement","entityId":"hisilicon-kirin-9030-pro","scope":"product-model","sourceUrl":"https://newsletter.semianalysis.com/p/steel-smic-n3-teardown","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"},{"key":"Verified die geometry","value":null,"sourceId":"huawei-mate80promax-specs","location":"Evidence review","evidenceClass":"unknown","note":"No source meeting calibrated geometry requirements accepted in this scout pass. Reported measurements, if present, remain separately labeled.","entityId":"hisilicon-kirin-9030-pro","scope":"product-model","sourceUrl":"https://consumer.huawei.com/cn/phones/mate80-pro-max/specs/","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"unresearched"}],"sources":["huawei-mate80promax-specs","huawei-mate80pro-specs","semianalysis-kirin9030-process","huawei-jdc-mate80-launch"],"url":"https://museum.vlsi.kr/objects/hisilicon-kirin-9030-pro"},{"id":"huawei-mate-20-teardown","name":"Huawei Mate 20 — teardown specimen","kind":"specimen","entityType":"physical-specimen","subtype":"specimen","company":"Huawei","year":null,"aliases":["Huawei Mate 20 — teardown specimen","Chipwise"],"fields":[],"sources":["chipwise-source-e493d326ffa4","chipwise-source-3396bc15c91e","chipwise-source-ef137f278313"],"url":"https://museum.vlsi.kr/objects/huawei-mate-20-teardown"},{"id":"hybrid-bonding","name":"Hybrid bonding & TSMC SoIC","kind":"packaging-technology","entityType":"concept","subtype":"packaging-technology","company":"TSMC","year":null,"aliases":["SoIC","3D integration","hybrid bonding","Cu-Cu bonding","하이브리드 본딩"],"fields":[{"key":"Integration","value":"Three-dimensional chiplet integration","sourceId":"launch-tsmc-soic","location":"Technical overview / terminology","evidenceClass":"official-disclosure","entityId":"hybrid-bonding","scope":"concept","sourceUrl":"https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm","sourceDate":null,"retrievedAt":"2026-09-07","researchState":"sourced"},{"key":"Platform","value":"TSMC SoIC","sourceId":"launch-tsmc-soic","location":"Technical overview / terminology","evidenceClass":"official-disclosure","entityId":"hybrid-bonding","scope":"concept","sourceUrl":"https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm","sourceDate":null,"retrievedAt":"2026-09-07","researchState":"sourced"}],"sources":["launch-tsmc-soic"],"url":"https://museum.vlsi.kr/objects/hybrid-bonding"},{"id":"ibm-power10","name":"IBM POWER10","kind":"silicon-design","entityType":"silicon-die","subtype":"cpu","company":"IBM","year":2020,"architecture":"POWER","process":"7 nm","aliases":[],"fields":[{"key":"Record year","value":2020,"unit":"","sourceId":"ibm-power10","location":"announced; systems expected in 2021","variant":"processor design","note":"Year basis: announced; systems expected in 2021. This is distinct from source publication and record update.","entityId":"ibm-power10","scope":"processor design","sourceUrl":"https://hongkong.newsroom.ibm.com/news-releases?item=122398","sourceDate":"2020-08-17","retrievedAt":"2026-09-05","researchState":"sourced","evidenceClass":"official-disclosure"},{"key":"Process label","value":7,"unit":"nm","sourceId":"ibm-power10","location":"IBM POWER10 7nm Form Factor Delivers Energy Efficiency and Capacity Gains","variant":"processor design","evidenceClass":"official-disclosure","note":"","entityId":"ibm-power10","scope":"processor design","sourceUrl":"https://hongkong.newsroom.ibm.com/news-releases?item=122398","sourceDate":"2020-08-17","retrievedAt":"2026-09-05","researchState":"sourced"},{"key":"AI engine","value":"Matrix Math Accelerator","unit":"","sourceId":"ibm-power10","location":"Infusing AI into the Enterprise Hybrid Cloud","variant":"processor design","evidenceClass":"official-disclosure","note":"","entityId":"ibm-power10","scope":"processor design","sourceUrl":"https://hongkong.newsroom.ibm.com/news-releases?item=122398","sourceDate":"2020-08-17","retrievedAt":"2026-09-05","researchState":"sourced"},{"key":"Memory encryption","value":"Hardware-supported","unit":"","sourceId":"ibm-power10","location":"Hardware Enhancements to Further Secure the Hybrid Cloud","variant":"processor design","evidenceClass":"official-disclosure","note":"","entityId":"ibm-power10","scope":"processor design","sourceUrl":"https://hongkong.newsroom.ibm.com/news-releases?item=122398","sourceDate":"2020-08-17","retrievedAt":"2026-09-05","researchState":"sourced"},{"key":"Die area","value":602,"unit":"mm²","sourceId":"geometry-ibm-power10-blis2020","location":"POWER10 Hardware Specs, first bullet; web text lines 24–26","variant":"One POWER10 silicon die","evidenceClass":"official-disclosure","note":"Original IBM/CMU speaker page at BLIS Retreat 2020; area excludes the single/dual-chip socket or module. Public IBM Redbooks search extracts independently corroborate 602 mm², but no PDF was downloaded.","entityId":"ibm-power10","scope":"One POWER10 silicon die","sourceUrl":"https://www.cs.utexas.edu/~flame/BLISRetreat2020/Nicholai.html","sourceDate":null,"retrievedAt":"2026-09-06","researchState":"sourced"}],"sources":["ibm-power10","geometry-ibm-power10-blis2020"],"url":"https://museum.vlsi.kr/objects/ibm-power10"},{"id":"ibm-telum","name":"IBM Telum","kind":"silicon-design","entityType":"silicon-die","subtype":"cpu","company":"IBM","year":2021,"process":"7 nm","aliases":[],"fields":[{"key":"Record year","value":2021,"unit":"","sourceId":"ibm-telum-release","location":"announced","variant":"one central-processor die, not the dual-chip module","note":"Year basis: announced. This is distinct from source publication and record update.","entityId":"ibm-telum","scope":"one central-processor die, not the dual-chip module","sourceUrl":"https://newsroom.ibm.com/2021-08-23-IBM-Unveils-On-Chip-Accelerated-Artificial-Intelligence-Processor?asPDF=1","sourceDate":"2021-08-23","retrievedAt":"2026-09-05","researchState":"sourced","evidenceClass":"official-disclosure"},{"key":"CPU cores per die","value":8,"unit":"cores","sourceId":"ibm-telum-paper","location":"Abstract — each CP","variant":"one central-processor die, not the dual-chip module","evidenceClass":"official-disclosure","note":"The ISSCC abstract explicitly reports 22B per CP die; the 2021 press release uses ambiguous dual-chip-module wording.","entityId":"ibm-telum","scope":"one central-processor die, not the dual-chip module","sourceUrl":"https://research.ibm.com/publications/ibm-telum-a-16-core-5-ghz-dcm","sourceDate":"2022-02-19","retrievedAt":"2026-09-05","researchState":"sourced"},{"key":"Transistors per die","value":22,"unit":"billion transistors","sourceId":"ibm-telum-paper","location":"Abstract — each CP contains 22B transistors","variant":"one central-processor die, not the dual-chip module","evidenceClass":"official-disclosure","note":"22 billion is per CP die in the ISSCC abstract. The press release refers to a dual-chip module; do not treat that module count as a per-die claim.","entityId":"ibm-telum","scope":"one central-processor die, not the dual-chip module","sourceUrl":"https://research.ibm.com/publications/ibm-telum-a-16-core-5-ghz-dcm","sourceDate":"2022-02-19","retrievedAt":"2026-09-05","researchState":"sourced"},{"key":"Die area","value":530,"unit":"mm²","sourceId":"geometry-ibm-telum-isscc2022","location":"Abstract, sentence beginning The CP die size; web text line 11","variant":"One first-generation Telum central-processor die (CP)","evidenceClass":"official-disclosure","note":"Each dual-chip module contains two CP dies. 530 mm² is one die, not the 16-core DCM total.","entityId":"ibm-telum","scope":"One first-generation Telum central-processor die (CP)","sourceUrl":"https://research.ibm.com/publications/ibm-telum-a-16-core-5-ghz-dcm","sourceDate":"2022-02-19","retrievedAt":"2026-09-06","researchState":"sourced"},{"key":"Process label","value":7,"unit":"nm","sourceId":"ibm-telum-paper","location":"Abstract — 7nm bulk technology","variant":"one central-processor die, not the dual-chip module","evidenceClass":"official-disclosure","note":"The ISSCC abstract explicitly reports 22B per CP die; the 2021 press release uses ambiguous dual-chip-module wording.","entityId":"ibm-telum","scope":"one central-processor die, not the dual-chip module","sourceUrl":"https://research.ibm.com/publications/ibm-telum-a-16-core-5-ghz-dcm","sourceDate":"2022-02-19","retrievedAt":"2026-09-05","researchState":"sourced"}],"sources":["ibm-telum-release","ibm-telum-paper","geometry-ibm-telum-isscc2022"],"url":"https://museum.vlsi.kr/objects/ibm-telum"},{"id":"implementation-ibm-45nm-soi-cmos-iedm2006","name":"IBM 45-nm SOI CMOS technology","kind":"device","entityType":"process-variant","subtype":"soi-cmos","company":"IBM","year":2006,"aliases":[],"fields":[{"key":"Device family","value":"SOI CMOS","unit":"","conditions":"","location":"Abstract","sourceId":"src-ibm-45nm-soi","evidenceClass":"official-disclosure","entityId":"implementation-ibm-45nm-soi-cmos-iedm2006","scope":"process-variant","sourceUrl":"https://research.ibm.com/publications/high-performance-45-nm-soi-technology-with-enhanced-strain-porous-low-k-beol-and-immersion-lithography","sourceDate":"2006-12-01","retrievedAt":"2026-09-14T16:27:48Z","researchState":"sourced"},{"key":"Substrate","value":"silicon-on-insulator","unit":"","conditions":"","location":"Abstract","sourceId":"src-ibm-45nm-soi","evidenceClass":"official-disclosure","entityId":"implementation-ibm-45nm-soi-cmos-iedm2006","scope":"process-variant","sourceUrl":"https://research.ibm.com/publications/high-performance-45-nm-soi-technology-with-enhanced-strain-porous-low-k-beol-and-immersion-lithography","sourceDate":"2006-12-01","retrievedAt":"2026-09-14T16:27:48Z","researchState":"sourced"},{"key":"Application","value":"high-performance CMOS","unit":"","conditions":"","location":"Abstract","sourceId":"src-ibm-45nm-soi","evidenceClass":"official-disclosure","entityId":"implementation-ibm-45nm-soi-cmos-iedm2006","scope":"process-variant","sourceUrl":"https://research.ibm.com/publications/high-performance-45-nm-soi-technology-with-enhanced-strain-porous-low-k-beol-and-immersion-lithography","sourceDate":"2006-12-01","retrievedAt":"2026-09-14T16:27:48Z","researchState":"sourced"},{"key":"Ground-rule technology","value":45,"unit":"nm","conditions":"","location":"Abstract","sourceId":"src-ibm-45nm-soi","evidenceClass":"official-disclosure","entityId":"implementation-ibm-45nm-soi-cmos-iedm2006","scope":"process-variant","sourceUrl":"https://research.ibm.com/publications/high-performance-45-nm-soi-technology-with-enhanced-strain-porous-low-k-beol-and-immersion-lithography","sourceDate":"2006-12-01","retrievedAt":"2026-09-14T16:27:48Z","researchState":"sourced"},{"key":"Supply voltage for reported Idsat","value":1,"unit":"V","conditions":"","location":"Abstract","sourceId":"src-ibm-45nm-soi","evidenceClass":"official-disclosure","entityId":"implementation-ibm-45nm-soi-cmos-iedm2006","scope":"process-variant","sourceUrl":"https://research.ibm.com/publications/high-performance-45-nm-soi-technology-with-enhanced-strain-porous-low-k-beol-and-immersion-lithography","sourceDate":"2006-12-01","retrievedAt":"2026-09-14T16:27:48Z","researchState":"sourced"},{"key":"PFET saturation drive current","value":840,"unit":"µA/µm","conditions":"VDD=1.0 V; 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1.2 GHz core / 935 MHz controller","sourceId":"specs-gamma2600","location":"Exynos 2600 — NPU","evidenceClass":"third-party-report","state":"known","confidence":"medium","entityId":"samsung-exynos-2600","scope":"silicon-die","sourceUrl":"https://gamma0burst.tistory.com/413258","sourceDate":"2026-03-25","retrievedAt":"2026-09-09","researchState":"sourced"},{"key":"Reported modem pairing","value":"External S5410","sourceId":"specs-gamma2600","location":"Exynos 2600 — modem paragraph","evidenceClass":"third-party-report","state":"known","confidence":"medium","note":"The analyst reports an S5410 pairing and no integrated-modem entry in the examined kernel.","entityId":"samsung-exynos-2600","scope":"silicon-die","sourceUrl":"https://gamma0burst.tistory.com/413258","sourceDate":"2026-03-25","retrievedAt":"2026-09-09","researchState":"sourced"},{"key":"Estimated CPU complex area","value":27.95,"sourceId":"specs-reptalica-2600","location":"Reptalica post of 2026-04-25, embedded in the Vengineer article","evidenceClass":"third-party-report","state":"estimated","note":"Die-photo annotation; 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