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Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/500AFX","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/500AFX","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 26, 1999","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 11, 1999","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":499.99,"unit":"MHz","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8336-r26031","location":"Amd/k6-2/k6-2-500afx · revision 26031 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-000322e7a6b05045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500afx&oldid=26031","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8336-r26031"],"url":"https://museum.vlsi.kr/objects/cw-000322e7a6b05045"},{"id":"cw-001905b4201f3fde","name":"R80186-6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1985,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 r80186-6"],"fields":[{"key":"Model name","value":"R80186-6","unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"R80186-6","unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"R80186-6","unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1985,"unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":6,"unit":"MHz","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"1.5 MT/s","unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CLCC-68","unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CLCC","unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CLCC-68","unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8624-r26822","location":"Amd/am186/r80186-6 · revision 26822 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-001905b4201f3fde","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fr80186-6&oldid=26822","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8624-r26822"],"url":"https://museum.vlsi.kr/objects/cw-001905b4201f3fde"},{"id":"cw-003070d5c75362d3","name":"EPYC 7301","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7000","year":2017,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc 7301"],"fields":[{"key":"Model name","value":"EPYC 7301","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7301,"unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PS7301BEVGPAF","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7000,"unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2700,"unit":"MHz","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Naples","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":19200000000,"unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":155,"unit":"W","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x64 KiB","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x512 KiB","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x8 MiB","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-5070-r16542","location":"Amd/epyc/7301 · revision 16542 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7301&oldid=16542","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-4094","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket SP3","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-003070d5c75362d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5070-r16542","chipswiki-31468-r92417"],"url":"https://museum.vlsi.kr/objects/cw-003070d5c75362d3"},{"id":"cw-0058a5267f9d871a","name":"Core i5-1035G7","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-10000","year":2019,"architecture":"Ice Lake (Client)","process":"10 nm","aliases":["Intel core i5 i5-1035g7"],"fields":[{"key":"Model name","value":"Core i5-1035G7","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-1035G7","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-10000","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ice Lake (Client)","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Ice Lake","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ice Lake U","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x48 KiB","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":55.63,"unit":"GiB/s","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Plus Graphics","unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":64,"unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-1256-r4082","location":"Intel/core i5/i5-1035g7 · revision 4082 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-0058a5267f9d871a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g7&oldid=4082","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1256-r4082"],"url":"https://museum.vlsi.kr/objects/cw-0058a5267f9d871a"},{"id":"cw-00813bda2639f4bf","name":"CN3120-550 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3120-550bg868-exp"],"fields":[{"key":"Model name","value":"Cavium CN3120-550 EXP","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3120-550 EXP","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":550,"unit":"MHz","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8240-r25900","location":"Cavium/octeon/cn3120-550bg868-exp · revision 25900 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-exp&oldid=25900","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00813bda2639f4bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8240-r25900","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-00813bda2639f4bf"},{"id":"cw-00832f25a84ddcc2","name":"VL86C020","kind":"sku","entityType":"product-model","subtype":"soc","company":"Acorn","year":1989,"architecture":"ARM3","process":"1.5 µm","aliases":["Vti vl86cx vl86c020"],"fields":[{"key":"Model name","value":"VL86C020","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Acorn Computers","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Sanyo","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"VL86C020","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VL86C020-20FC","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VL86C020-20GC","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C020-20FC","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C020-20GC","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C020-25FC","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C020-35PSGC","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / part number 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 6","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"part number 6","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1989,"unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"VL86Cx","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":20,"unit":"MHz","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":25,"unit":"MHz","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":33,"unit":"MHz","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 4","value":36,"unit":"MHz","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / frequency 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 4","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"Multiple clock domains; raw parameter frequency 4","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv2a","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM3","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MEMC","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":309656,"unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":86.764,"unit":"mm²","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"MiB","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4,"unit":"KiB","sourceId":"chipswiki-572-r1231","location":"Vti/vl86cx/vl86c020 · revision 1231 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c020&oldid=1231","sourceDate":"2021-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"PQFP-160","unit":"","sourceId":"chipswiki-31442-r92368","location":"Template:Packages/vti/pqfp-160 · revision 92368 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2021-11-07. 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Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fpqfp-160&oldid=92368","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"PGA-144","unit":"","sourceId":"chipswiki-31440-r92362","location":"Template:Packages/vti/pga-144 · revision 92362 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2021-11-07. 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Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fpga-144&oldid=92362","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":28.1,"unit":"mm","sourceId":"chipswiki-31440-r92362","location":"Template:Packages/vti/pga-144 · revision 92362 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fpga-144&oldid=92362","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":3.85,"unit":"mm","sourceId":"chipswiki-31440-r92362","location":"Template:Packages/vti/pga-144 · revision 92362 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2021-11-07. Not an independent measurement.","entityId":"cw-00832f25a84ddcc2","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fpga-144&oldid=92362","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-572-r1231","chipswiki-31442-r92368","chipswiki-31440-r92362"],"url":"https://museum.vlsi.kr/objects/cw-00832f25a84ddcc2"},{"id":"cw-00888610c053c3b5","name":"Pentium N3700","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N3000","year":2015,"architecture":"Airmont","process":"14 nm","aliases":["Intel pentium (2009) n3700"],"fields":[{"key":"Model name","value":"Pentium N3700","unit":"","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N3700","unit":"","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066501715906","unit":"","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066501715923","unit":"","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR29E","unit":"","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. 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Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March, 2015","unit":"","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. 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Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. 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Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-6862-r21415","location":"Intel/pentium (2009)/n3700 · revision 21415 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-00888610c053c3b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3700&oldid=21415","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6862-r21415"],"url":"https://museum.vlsi.kr/objects/cw-00888610c053c3b5"},{"id":"cw-008cb11d6cdf8468","name":"Kirin 990 5G","kind":"sku","entityType":"product-model","subtype":"soc","company":"HiSilicon","year":2019,"architecture":"Cortex-A76","process":"7 nm+ EUV","aliases":["Kirin 990"],"fields":[{"key":"Model name","value":"Kirin 990 5G","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"HiSilicon","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"990 5G","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 6, 2019","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 6, 2019","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Kirin","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2860,"unit":"MHz","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2360,"unit":"MHz","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":1950,"unit":"MHz","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A76","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A76","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A55","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+ EUV","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":10300000000,"unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":113.31,"unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","alternatives":[{"value":"113.31 mm²","sourceId":"chipswiki-348-r731","reason":"Kirin 990 · revision 731 · {{chip}} / die size. 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Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":512,"unit":"KiB","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":2,"unit":"MiB","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"4x512 KiB","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":256,"unit":"KiB","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 2)","value":"4x32 KiB","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 2)","value":"4x32 KiB","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":512,"unit":"KiB","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"4x128 KiB","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-4266","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G76","unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":16,"unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":600,"unit":"MHz","sourceId":"chipswiki-348-r731","location":"Kirin 990 · revision 731 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-26. Not an independent measurement.","entityId":"cw-008cb11d6cdf8468","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990&oldid=731","sourceDate":"2022-05-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-348-r731"],"url":"https://museum.vlsi.kr/objects/cw-008cb11d6cdf8468"},{"id":"cw-009557a41f687959","name":"K6-2E+/400ICR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2+ Embedded","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-2+ k6-2e+-400icr"],"fields":[{"key":"Model name","value":"K6-2E+/400ICR","unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E+/400ICR","unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E+/400ICR","unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":16.5,"unit":"W","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2+","unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2+ Embedded","unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"100 MT/s","unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":5,"unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":6,"unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":7,"unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. 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Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. 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Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1003-r2854","location":"Amd/k6-2+/k6-2e+-400icr · revision 2854 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400icr&oldid=2854","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OBGA-349","unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":349,"unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":25,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.47,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-009557a41f687959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1003-r2854","chipswiki-31127-r91599"],"url":"https://museum.vlsi.kr/objects/cw-009557a41f687959"},{"id":"cw-00ad4c914b8647f2","name":"Au1","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Alchemy","year":2000,"process":"180 nm","aliases":["Alchemy microarchitectures au1"],"fields":[{"key":"Architecture name","value":"Au1","unit":"","sourceId":"chipswiki-369-r813","location":"Alchemy/microarchitectures/au1 · revision 813 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-17. 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Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25180000,"unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":105.68,"unit":"mm²","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.75,"unit":"V","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":60,"unit":"W","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8425-r26133","location":"Amd/duron/dhd1300amt1b · revision 26133 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00bd862f188d9ca4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1300amt1b&oldid=26133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8425-r26133"],"url":"https://museum.vlsi.kr/objects/cw-00bd862f188d9ca4"},{"id":"cw-00c56ff64bcbd1a9","name":"Cortex-A12","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2013,"aliases":["Arm holdings microarchitectures cortex-a12"],"fields":[{"key":"Architecture name","value":"Cortex-A12","unit":"","sourceId":"chipswiki-4150-r13227","location":"Arm holdings/microarchitectures/cortex-a12 · revision 13227 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-00c56ff64bcbd1a9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a12&oldid=13227","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-4150-r13227","location":"Arm holdings/microarchitectures/cortex-a12 · revision 13227 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-00c56ff64bcbd1a9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a12&oldid=13227","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4150-r13227","location":"Arm holdings/microarchitectures/cortex-a12 · revision 13227 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-00c56ff64bcbd1a9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a12&oldid=13227","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"June 2, 2013","unit":"","sourceId":"chipswiki-4150-r13227","location":"Arm holdings/microarchitectures/cortex-a12 · revision 13227 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-00c56ff64bcbd1a9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a12&oldid=13227","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-4150-r13227","location":"Arm holdings/microarchitectures/cortex-a12 · revision 13227 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-00c56ff64bcbd1a9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a12&oldid=13227","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A9","unit":"","sourceId":"chipswiki-4150-r13227","location":"Arm holdings/microarchitectures/cortex-a12 · revision 13227 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. 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Not an independent measurement.","entityId":"cw-00c56ff64bcbd1a9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a12&oldid=13227","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4150-r13227"],"url":"https://museum.vlsi.kr/objects/cw-00c56ff64bcbd1a9"},{"id":"cw-00e2f30dff4a2359","name":"Xeon E3-1565L v5","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1500 v5","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel xeon e3 e3-1565l v5"],"fields":[{"key":"Model name","value":"Xeon E3-1565L v5","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1565L v5","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2R8","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 31, 2016","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 31, 2016","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1500 v5","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"N0","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Pro Graphics P580","unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":72,"unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-7755-r25137","location":"Intel/xeon e3/e3-1565l v5 · revision 25137 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1565l%20v5&oldid=25137","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00e2f30dff4a2359","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7755-r25137","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-00e2f30dff4a2359"},{"id":"cw-00eec1e91029d77b","name":"Alchemy Au1200-400MGD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2005,"architecture":"Au1","aliases":["Alchemy au1200-400mgd"],"fields":[{"key":"Model name","value":"Alchemy Au1200-400MGD","unit":"","sourceId":"chipswiki-453-r934","location":"Alchemy/au1200-400mgd · revision 934 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-00eec1e91029d77b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgd&oldid=934","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-453-r934","location":"Alchemy/au1200-400mgd · revision 934 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-00eec1e91029d77b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgd&oldid=934","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1200-400MGD","unit":"","sourceId":"chipswiki-453-r934","location":"Alchemy/au1200-400mgd · revision 934 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-00eec1e91029d77b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgd&oldid=934","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-453-r934","location":"Alchemy/au1200-400mgd · revision 934 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-00eec1e91029d77b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgd&oldid=934","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2005","unit":"","sourceId":"chipswiki-453-r934","location":"Alchemy/au1200-400mgd · revision 934 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-00eec1e91029d77b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgd&oldid=934","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-453-r934","location":"Alchemy/au1200-400mgd · revision 934 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-00eec1e91029d77b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgd&oldid=934","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-453-r934","location":"Alchemy/au1200-400mgd · revision 934 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-00eec1e91029d77b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgd&oldid=934","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-453-r934","location":"Alchemy/au1200-400mgd · revision 934 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-00eec1e91029d77b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgd&oldid=934","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-453-r934","location":"Alchemy/au1200-400mgd · revision 934 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-00eec1e91029d77b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgd&oldid=934","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.600 GB/s","unit":"","sourceId":"chipswiki-453-r934","location":"Alchemy/au1200-400mgd · revision 934 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-00eec1e91029d77b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgd&oldid=934","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-453-r934"],"url":"https://museum.vlsi.kr/objects/cw-00eec1e91029d77b"},{"id":"cw-00fb1e537f2884dd","name":"AM9080A-2DMB","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080a-2dmb"],"fields":[{"key":"Model name","value":"AMD AM9080A-2DMB","unit":"","sourceId":"chipswiki-8477-r26670","location":"Amd/am9080/am9080a-2dmb · revision 26670 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00fb1e537f2884dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dmb&oldid=26670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8477-r26670","location":"Amd/am9080/am9080a-2dmb · revision 26670 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00fb1e537f2884dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dmb&oldid=26670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8477-r26670","location":"Amd/am9080/am9080a-2dmb · revision 26670 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00fb1e537f2884dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dmb&oldid=26670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080A-2DMB","unit":"","sourceId":"chipswiki-8477-r26670","location":"Amd/am9080/am9080a-2dmb · revision 26670 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00fb1e537f2884dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dmb&oldid=26670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080A-2DMB","unit":"","sourceId":"chipswiki-8477-r26670","location":"Amd/am9080/am9080a-2dmb · revision 26670 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00fb1e537f2884dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dmb&oldid=26670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Military","unit":"","sourceId":"chipswiki-8477-r26670","location":"Amd/am9080/am9080a-2dmb · revision 26670 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00fb1e537f2884dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dmb&oldid=26670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8477-r26670","location":"Amd/am9080/am9080a-2dmb · revision 26670 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00fb1e537f2884dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dmb&oldid=26670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8477-r26670","location":"Amd/am9080/am9080a-2dmb · revision 26670 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-00fb1e537f2884dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dmb&oldid=26670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.632,"unit":"MHz","sourceId":"chipswiki-8477-r26670","location":"Amd/am9080/am9080a-2dmb · revision 26670 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00fb1e537f2884dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dmb&oldid=26670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8477-r26670","location":"Amd/am9080/am9080a-2dmb · revision 26670 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-00fb1e537f2884dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dmb&oldid=26670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8477-r26670","location":"Amd/am9080/am9080a-2dmb · revision 26670 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00fb1e537f2884dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dmb&oldid=26670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8477-r26670","location":"Amd/am9080/am9080a-2dmb · revision 26670 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-00fb1e537f2884dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dmb&oldid=26670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8477-r26670","location":"Amd/am9080/am9080a-2dmb · revision 26670 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1483-r4931","location":"Intel/xeon gold/6240y · revision 4931 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-00feb07ee5fc751e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240y&oldid=4931","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1483-r4931"],"url":"https://museum.vlsi.kr/objects/cw-00feb07ee5fc751e"},{"id":"cw-0101a33226fec860","name":"NNP-T 1300","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"NNP-T","year":2019,"architecture":"Spring Crest","process":"16 nm","aliases":["Nervana nnp nnp-t 1300"],"fields":[{"key":"Model name","value":"NNP-T 1300","unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"NNP-T 1300","unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 12, 2019","unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 12, 2019","unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"NNP","unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"NNP-T","unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":950,"unit":"MHz","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Spring Crest","unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":27000000000,"unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":680,"unit":"mm²","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":22,"unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":300,"unit":"W","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"HBM2-2400","unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":32,"unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.2288 TB/s","unit":"","sourceId":"chipswiki-1364-r4500","location":"Nervana/nnp/nnp-t 1300 · revision 4500 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-0101a33226fec860","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201300&oldid=4500","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1364-r4500"],"url":"https://museum.vlsi.kr/objects/cw-0101a33226fec860"},{"id":"cw-0102513b7f1569e8","name":"i486SX2-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486SX2","year":null,"architecture":"80486","process":"800 nm","aliases":["Intel 80486 486sx2-66"],"fields":[{"key":"Model name","value":"Intel i486SX2-66","unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486SX2-66","unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486SX2-66","unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486SX2","unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":66,"unit":"MHz","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SX2","unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":900000,"unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8076-r25727","location":"Intel/80486/486sx2-66 · revision 25727 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0102513b7f1569e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-66&oldid=25727","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8076-r25727"],"url":"https://museum.vlsi.kr/objects/cw-0102513b7f1569e8"},{"id":"cw-015d946c5821bd36","name":"Core i9-9880H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i9-9000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i9 i9-9880h"],"fields":[{"key":"Model name","value":"Core i9-9880H","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i9-9880H","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8068404069006","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFD1","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i9","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i9-9000","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4800,"unit":"MHz","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. 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Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-1085-r3161","location":"Intel/core i9/i9-9880h · revision 3161 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. Not an independent measurement.","entityId":"cw-015d946c5821bd36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9880h&oldid=3161","sourceDate":"2020-06-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-12. 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Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-6442EQ","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-6000","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2700,"unit":"MHz","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7919-r25457","location":"Intel/core i5/i5-6442eq · revision 25457 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6442eq&oldid=25457","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0170e4a91ccee923","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7919-r25457","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-0170e4a91ccee923"},{"id":"cw-0194a5f1ff6900cb","name":"Core i3-1000G1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-10000","year":2019,"architecture":"Ice Lake (Client)","process":"10 nm","aliases":["Intel core i3 i3-1000g1"],"fields":[{"key":"Model name","value":"Core i3-1000G1","unit":"","sourceId":"chipswiki-1237-r3945","location":"Intel/core i3/i3-1000g1 · revision 3945 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. 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Not an independent measurement.","entityId":"cw-0194a5f1ff6900cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g1&oldid=3945","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1237-r3945","location":"Intel/core i3/i3-1000g1 · revision 3945 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. 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Not an independent measurement.","entityId":"cw-0194a5f1ff6900cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g1&oldid=3945","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-1237-r3945","location":"Intel/core i3/i3-1000g1 · revision 3945 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. 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Not an independent measurement.","entityId":"cw-0194a5f1ff6900cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g1&oldid=3945","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1237-r3945","location":"Intel/core i3/i3-1000g1 · revision 3945 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-0194a5f1ff6900cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g1&oldid=3945","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-1237-r3945","location":"Intel/core i3/i3-1000g1 · revision 3945 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-0194a5f1ff6900cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g1&oldid=3945","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-1237-r3945","location":"Intel/core i3/i3-1000g1 · revision 3945 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. 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Not an independent measurement.","entityId":"cw-0194a5f1ff6900cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g1&oldid=3945","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x48 KiB","unit":"","sourceId":"chipswiki-1237-r3945","location":"Intel/core i3/i3-1000g1 · revision 3945 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. 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Not an independent measurement.","entityId":"cw-0194a5f1ff6900cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g1&oldid=3945","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-1237-r3945","location":"Intel/core i3/i3-1000g1 · revision 3945 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. 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Not an independent measurement.","entityId":"cw-0194a5f1ff6900cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g1&oldid=3945","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1237-r3945","location":"Intel/core i3/i3-1000g1 · revision 3945 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-0194a5f1ff6900cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g1&oldid=3945","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-1237-r3945","location":"Intel/core i3/i3-1000g1 · revision 3945 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. 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Not an independent measurement.","entityId":"cw-0194a5f1ff6900cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g1&oldid=3945","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-1237-r3945","location":"Intel/core i3/i3-1000g1 · revision 3945 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. 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Not an independent measurement.","entityId":"cw-0194a5f1ff6900cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1000g1&oldid=3945","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1237-r3945","location":"Intel/core i3/i3-1000g1 · revision 3945 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. 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Not an independent measurement.","entityId":"cw-01a0587c63c77467","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-8&oldid=26789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8591-r26789","location":"Amd/am286/n80c286-8 · revision 26789 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01a0587c63c77467","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-8&oldid=26789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8591-r26789","location":"Amd/am286/n80c286-8 · revision 26789 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01a0587c63c77467","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-8&oldid=26789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8591-r26789","location":"Amd/am286/n80c286-8 · revision 26789 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01a0587c63c77467","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-8&oldid=26789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8591-r26789","location":"Amd/am286/n80c286-8 · revision 26789 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01a0587c63c77467","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-8&oldid=26789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8591-r26789","location":"Amd/am286/n80c286-8 · revision 26789 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01a0587c63c77467","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-8&oldid=26789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":165,"unit":"°C","sourceId":"chipswiki-8591-r26789","location":"Amd/am286/n80c286-8 · revision 26789 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01a0587c63c77467","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-8&oldid=26789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-68","unit":"","sourceId":"chipswiki-8591-r26789","location":"Amd/am286/n80c286-8 · revision 26789 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01a0587c63c77467","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-8&oldid=26789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8591-r26789","location":"Amd/am286/n80c286-8 · revision 26789 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01a0587c63c77467","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-8&oldid=26789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PLCC-68","unit":"","sourceId":"chipswiki-8591-r26789","location":"Amd/am286/n80c286-8 · revision 26789 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01a0587c63c77467","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-8&oldid=26789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8591-r26789","location":"Amd/am286/n80c286-8 · revision 26789 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01a0587c63c77467","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-8&oldid=26789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8591-r26789","location":"Amd/am286/n80c286-8 · revision 26789 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01a0587c63c77467","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-8&oldid=26789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8591-r26789","location":"Amd/am286/n80c286-8 · revision 26789 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01a0587c63c77467","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-8&oldid=26789","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8591-r26789"],"url":"https://museum.vlsi.kr/objects/cw-01a0587c63c77467"},{"id":"cw-01c8852be29408f0","name":"Lake Crest","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Nervana","year":2016,"process":"28 nm","aliases":["Nervana microarchitectures lake crest"],"fields":[{"key":"Architecture name","value":"Lake Crest","unit":"","sourceId":"chipswiki-985-r2801","location":"Nervana/microarchitectures/lake crest · revision 2801 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-06. Not an independent measurement.","entityId":"cw-01c8852be29408f0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fmicroarchitectures%2Flake%20crest&oldid=2801","sourceDate":"2020-08-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Nervana","unit":"","sourceId":"chipswiki-985-r2801","location":"Nervana/microarchitectures/lake crest · revision 2801 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-06. Not an independent measurement.","entityId":"cw-01c8852be29408f0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fmicroarchitectures%2Flake%20crest&oldid=2801","sourceDate":"2020-08-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-985-r2801","location":"Nervana/microarchitectures/lake crest · revision 2801 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-06. Not an independent measurement.","entityId":"cw-01c8852be29408f0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fmicroarchitectures%2Flake%20crest&oldid=2801","sourceDate":"2020-08-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"November 17, 2016","unit":"","sourceId":"chipswiki-985-r2801","location":"Nervana/microarchitectures/lake crest · revision 2801 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-06. Not an independent measurement.","entityId":"cw-01c8852be29408f0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fmicroarchitectures%2Flake%20crest&oldid=2801","sourceDate":"2020-08-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-985-r2801","location":"Nervana/microarchitectures/lake crest · revision 2801 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-06. Not an independent measurement.","entityId":"cw-01c8852be29408f0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fmicroarchitectures%2Flake%20crest&oldid=2801","sourceDate":"2020-08-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Spring Crest","unit":"","sourceId":"chipswiki-985-r2801","location":"Nervana/microarchitectures/lake crest · revision 2801 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-06. Not an independent measurement.","entityId":"cw-01c8852be29408f0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fmicroarchitectures%2Flake%20crest&oldid=2801","sourceDate":"2020-08-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-985-r2801"],"url":"https://museum.vlsi.kr/objects/cw-01c8852be29408f0"},{"id":"cw-01d3341139f62b0c","name":"Pentium Gold G5400T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel pentium gold g5400t"],"fields":[{"key":"Model name","value":"Pentium Gold G5400T","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G5400T","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403360212","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3XB","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium Gold","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":88,"unit":"°C","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 610","unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-6445-r20176","location":"Intel/pentium gold/g5400t · revision 20176 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-01d3341139f62b0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5400t&oldid=20176","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6445-r20176"],"url":"https://museum.vlsi.kr/objects/cw-01d3341139f62b0c"},{"id":"cw-01d672978365a8b4","name":"Core i7-8500Y","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-8000","year":2018,"architecture":"Amber Lake","process":"14 nm","aliases":["Intel core i7 i7-8500y"],"fields":[{"key":"Model name","value":"Core i7-8500Y","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-8500Y","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8067702739858","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRD21","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 28, 2018","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 28, 2018","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-8000","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Amber Lake","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Amber Lake","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Amber Lake Y","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":5,"unit":"W","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 615","unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-2480-r8475","location":"Intel/core i7/i7-8500y · revision 8475 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-01d672978365a8b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8500y&oldid=8475","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2480-r8475"],"url":"https://museum.vlsi.kr/objects/cw-01d672978365a8b4"},{"id":"cw-01df64ba2869564b","name":"Atom x5-Z8500","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z8000","year":2015,"architecture":"Airmont","process":"14 nm","aliases":["Intel atom x5 x5-z8500"],"fields":[{"key":"Model name","value":"Intel Atom x5-Z8500","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"x5-Z8500","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066401715814","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066401715842","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 2, 2015","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 2, 2015","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom x5","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z8000","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1440,"unit":"MHz","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2240,"unit":"MHz","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR27N","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2GN","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Cherry Trail","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cherry Trail","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA1380","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-8043-r25675","location":"Intel/atom x5/x5-z8500 · revision 25675 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-01df64ba2869564b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8500&oldid=25675","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8043-r25675"],"url":"https://museum.vlsi.kr/objects/cw-01df64ba2869564b"},{"id":"cw-01f04c6084758f94","name":"Helio X10 M (MT6795M)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio X","year":2015,"architecture":"Cortex-A53","process":"28 nm","aliases":["Mediatek helio mt6795m"],"fields":[{"key":"Model name","value":"MediaTek Helio X10 M","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Helio X10 M","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6795M","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MTK6795M","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 15, 2014","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 27, 2015","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio X","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 4 AXI","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":125,"unit":"°C","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"MWPOP-1108","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"MWPOP","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR G6200","unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":550,"unit":"MHz","sourceId":"chipswiki-7404-r24002","location":"Mediatek/helio/mt6795m · revision 24002 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-12. Not an independent measurement.","entityId":"cw-01f04c6084758f94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6795m&oldid=24002","sourceDate":"2018-01-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7404-r24002"],"url":"https://museum.vlsi.kr/objects/cw-01f04c6084758f94"},{"id":"cw-021e8e6d21ff4611","name":"Xeon E7-2830","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E7-2800","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel xeon e7 e7-2830"],"fields":[{"key":"Model name","value":"Xeon E7-2830","unit":"","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-2830","unit":"","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80615005787AB","unit":"","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-2800","unit":"","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2133.33,"unit":"MHz","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC3J","unit":"","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A2","unit":"","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.35,"unit":"V","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-021e8e6d21ff4611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-2830&oldid=25076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7706-r25076","location":"Intel/xeon e7/e7-2830 · revision 25076 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-022195783c472c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4570r&oldid=25488","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7941-r25488","location":"Intel/core i5/i5-4570r · revision 25488 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-022195783c472c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4570r&oldid=25488","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7941-r25488","location":"Intel/core i5/i5-4570r · revision 25488 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-022195783c472c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4570r&oldid=25488","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7941-r25488","location":"Intel/core i5/i5-4570r · revision 25488 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-022195783c472c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4570r&oldid=25488","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7941-r25488","location":"Intel/core i5/i5-4570r · revision 25488 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-022195783c472c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4570r&oldid=25488","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7941-r25488","location":"Intel/core i5/i5-4570r · revision 25488 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":75,"unit":"W","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x256 KiB","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-023014b174941c0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2618l%20v4&oldid=25122","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x2.5 MiB","unit":"","sourceId":"chipswiki-7745-r25122","location":"Intel/xeon e5/e5-2618l v4 · revision 25122 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"VY86C610C","unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C610C","unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C610C-5","unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 23, 1994","unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"VL86Cx","unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv3","unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MEMC","unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM610","unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.6,"unit":"µm","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":358931,"unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":26,"unit":"mm²","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4,"unit":"KiB","sourceId":"chipswiki-7626-r24881","location":"Vti/vl86cx/vy86c610c · revision 24881 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610c&oldid=24881","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-144","unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":20,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":20,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0233ff5d80f57c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.6,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0246b51d53b142a8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsaltwell&oldid=27238","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-8767-r27238","location":"Intel/microarchitectures/saltwell · revision 27238 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. 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Not an independent measurement.","entityId":"cw-0246b51d53b142a8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsaltwell&oldid=27238","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":16,"unit":"","sourceId":"chipswiki-8767-r27238","location":"Intel/microarchitectures/saltwell · revision 27238 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-0246b51d53b142a8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsaltwell&oldid=27238","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8767-r27238","location":"Intel/microarchitectures/saltwell · revision 27238 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cores","note":"Source-reported parameter; source revision 2017-11-30. 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Not an independent measurement.","entityId":"cw-0246b51d53b142a8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsaltwell&oldid=27238","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cedarview","unit":"","sourceId":"chipswiki-8767-r27238","location":"Intel/microarchitectures/saltwell · revision 27238 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-0246b51d53b142a8","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsaltwell&oldid=27238","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cloverview","unit":"","sourceId":"chipswiki-8767-r27238","location":"Intel/microarchitectures/saltwell · revision 27238 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-0246b51d53b142a8","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsaltwell&oldid=27238","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Centerton","unit":"","sourceId":"chipswiki-8767-r27238","location":"Intel/microarchitectures/saltwell · revision 27238 · {{microarchitecture}} / core name 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 4","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-0246b51d53b142a8","scope":"core name 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsaltwell&oldid=27238","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Briarwood","unit":"","sourceId":"chipswiki-8767-r27238","location":"Intel/microarchitectures/saltwell · revision 27238 · {{microarchitecture}} / core name 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 5","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-0246b51d53b142a8","scope":"core name 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsaltwell&oldid=27238","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Berryville","unit":"","sourceId":"chipswiki-8767-r27238","location":"Intel/microarchitectures/saltwell · revision 27238 · {{microarchitecture}} / core name 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 6","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-0246b51d53b142a8","scope":"core name 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsaltwell&oldid=27238","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Bonnell","unit":"","sourceId":"chipswiki-8767-r27238","location":"Intel/microarchitectures/saltwell · revision 27238 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-0246b51d53b142a8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsaltwell&oldid=27238","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Silvermont","unit":"","sourceId":"chipswiki-8767-r27238","location":"Intel/microarchitectures/saltwell · revision 27238 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-0246b51d53b142a8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsaltwell&oldid=27238","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8767-r27238"],"url":"https://museum.vlsi.kr/objects/cw-0246b51d53b142a8"},{"id":"cw-02666f5d888ee75f","name":"Celeron 3855U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel celeron 3855u"],"fields":[{"key":"Model name","value":"Celeron 3855U","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3855U","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066201931008","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2EV","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2015","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 27, 2015","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 510","unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":900,"unit":"MHz","sourceId":"chipswiki-8037-r25669","location":"Intel/celeron/3855u · revision 25669 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3855u&oldid=25669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-02666f5d888ee75f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8037-r25669","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-02666f5d888ee75f"},{"id":"cw-0295bf37340b8910","name":"K6-2/500ACK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile P","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-500ack"],"fields":[{"key":"Model name","value":"K6-2/500ACK","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/500ACK","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/500ACK","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile P","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":499.99,"unit":"MHz","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8338-r26033","location":"Amd/k6-2/k6-2-500ack · revision 26033 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0295bf37340b8910","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ack&oldid=26033","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8338-r26033"],"url":"https://museum.vlsi.kr/objects/cw-0295bf37340b8910"},{"id":"cw-029b6e2b3513bbc4","name":"POWER9 02CY089","kind":"sku","entityType":"product-model","subtype":"cpu","company":"IBM","series":"POWER9","year":2017,"architecture":"POWER9","process":"14 nm","aliases":["Ibm power 02cy089"],"fields":[{"key":"Model name","value":"02CY089","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"02CY089","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"02CY089","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2017","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2017","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"POWER","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"POWER9","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3.5,"unit":"GHz","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3.8,"unit":"GHz","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v3.0B","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"POWER9","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sforza","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8000000000,"unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":693.37,"unit":"mm²","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":160,"unit":"W","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":85,"unit":"°C","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":80,"unit":"MiB","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x10 MiB","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-3943-r12575","location":"Ibm/power/02cy089 · revision 12575 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-029b6e2b3513bbc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy089&oldid=12575","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3943-r12575"],"url":"https://museum.vlsi.kr/objects/cw-029b6e2b3513bbc4"},{"id":"cw-02a59a4afbbd4301","name":"POWER8","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2013,"process":"22 nm","aliases":["Ibm microarchitectures power8"],"fields":[{"key":"Architecture name","value":"POWER8","unit":"","sourceId":"chipswiki-9922-r31546","location":"Ibm/microarchitectures/power8 · revision 31546 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-02a59a4afbbd4301","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8&oldid=31546","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-9922-r31546","location":"Ibm/microarchitectures/power8 · revision 31546 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-02a59a4afbbd4301","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8&oldid=31546","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-9922-r31546","location":"Ibm/microarchitectures/power8 · revision 31546 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-02a59a4afbbd4301","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8&oldid=31546","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"August, 2013","unit":"","sourceId":"chipswiki-9922-r31546","location":"Ibm/microarchitectures/power8 · revision 31546 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-02a59a4afbbd4301","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8&oldid=31546","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-9922-r31546","location":"Ibm/microarchitectures/power8 · revision 31546 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-02a59a4afbbd4301","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8&oldid=31546","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":4,"unit":"","sourceId":"chipswiki-9922-r31546","location":"Ibm/microarchitectures/power8 · revision 31546 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-02a59a4afbbd4301","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8&oldid=31546","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-9922-r31546","location":"Ibm/microarchitectures/power8 · revision 31546 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-02a59a4afbbd4301","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8&oldid=31546","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-9922-r31546","location":"Ibm/microarchitectures/power8 · revision 31546 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-02a59a4afbbd4301","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8&oldid=31546","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-9922-r31546","location":"Ibm/microarchitectures/power8 · revision 31546 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-02a59a4afbbd4301","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8&oldid=31546","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"POWER7+","unit":"","sourceId":"chipswiki-9922-r31546","location":"Ibm/microarchitectures/power8 · revision 31546 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-02a59a4afbbd4301","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8&oldid=31546","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"POWER8+","unit":"","sourceId":"chipswiki-9922-r31546","location":"Ibm/microarchitectures/power8 · revision 31546 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-02a59a4afbbd4301","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower8&oldid=31546","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-9922-r31546"],"url":"https://museum.vlsi.kr/objects/cw-02a59a4afbbd4301"},{"id":"cw-02c22f0334ba6c31","name":"Xeon E5-2682 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2682 v4"],"fields":[{"key":"Model name","value":"Xeon E5-2682 v4","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2682 v4","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002647700","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2K4","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7200000000,"unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":456.12,"unit":"mm²","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":120,"unit":"W","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x256 KiB","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":40,"unit":"MiB","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x2.5 MiB","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7728-r25103","location":"Intel/xeon e5/e5-2682 v4 · revision 25103 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-02c22f0334ba6c31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2682%20v4&oldid=25103","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7728-r25103"],"url":"https://museum.vlsi.kr/objects/cw-02c22f0334ba6c31"},{"id":"cw-03215a93ba99d377","name":"Ryzen 5 2600E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000","year":2018,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 5 2600e"],"fields":[{"key":"Model name","value":"Ryzen 5 2600E","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2600E","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD260EBHM6IAF","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 10, 2018","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 10, 2018","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2000,"unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Pinnacle Ridge","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x64 KiB","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x8 MiB","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-2846-r9551","location":"Amd/ryzen 5/2600e · revision 9551 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F2600e&oldid=9551","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-03215a93ba99d377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2846-r9551","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-03215a93ba99d377"},{"id":"cw-032e96e1901e1833","name":"Core i9-7960X","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i9-7900","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel core i9 i9-7960x"],"fields":[{"key":"Model name","value":"Core i9-7960X","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i9-7960X","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303734802","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3RR","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 30, 2017","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2017","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i9","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i9-7900","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-01-25. 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Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. 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Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Skylake","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake X","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":98,"unit":"°C","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-3936-r12538","location":"Intel/core i9/i9-7960x · revision 12538 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-25. Not an independent measurement.","entityId":"cw-032e96e1901e1833","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7960x&oldid=12538","sourceDate":"2019-01-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3936-r12538"],"url":"https://museum.vlsi.kr/objects/cw-032e96e1901e1833"},{"id":"cw-036242fc32a66f88","name":"AMD-K6-2/300BNZ-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-300bnz-66"],"fields":[{"key":"Model name","value":"K6-2/300BNZ-66","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/300BNZ-66","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/300BNZ-66","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":299.99,"unit":"MHz","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.8,"unit":"V","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CBGA-360","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CBGA","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-360","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8376-r26071","location":"Amd/k6-2/k6-2-300bnz-66 · revision 26071 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-036242fc32a66f88","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz-66&oldid=26071","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8376-r26071"],"url":"https://museum.vlsi.kr/objects/cw-036242fc32a66f88"},{"id":"cw-037496e2b8a2cb85","name":"Core M3-7Y30","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"m3-7Y","year":2016,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core m m3-7y30"],"fields":[{"key":"Model name","value":"Core M3-7Y30","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"M3-7Y30","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8067702739824","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2ZY","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR347","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core M3","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"m3-7Y","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2600,"unit":"MHz","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake Y","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 615","unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":900,"unit":"MHz","sourceId":"chipswiki-4979-r16101","location":"Intel/core m/m3-7y30 · revision 16101 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-037496e2b8a2cb85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y30&oldid=16101","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4979-r16101"],"url":"https://museum.vlsi.kr/objects/cw-037496e2b8a2cb85"},{"id":"cw-037aef0fb314bc51","name":"Xeon D-2161I","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-2000","year":2018,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon d d-2161i"],"fields":[{"key":"Model name","value":"Xeon D-2161I","unit":"","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-2161I","unit":"","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8067303534104","unit":"","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3ZN","unit":"","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-2000","unit":"","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16.5,"unit":"MiB","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.375 MiB","unit":"","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-7158-r22595","location":"Intel/xeon d/d-2161i · revision 22595 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2161i&oldid=22595","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-2518","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":2518,"unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":52.5,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-037aef0fb314bc51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7158-r22595","chipswiki-31304-r92006"],"url":"https://museum.vlsi.kr/objects/cw-037aef0fb314bc51"},{"id":"cw-03b6871ece53d3bd","name":"VL2333","kind":"sku","entityType":"product-model","subtype":"soc","company":"Acorn","year":1986,"architecture":"ARM2","process":"2 µm","aliases":["Vti vl86cx vl2333"],"fields":[{"key":"Model name","value":"VL2333","unit":"","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Acorn Computers","unit":"","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"VL2333","unit":"","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VL2333-QC","unit":"","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1986,"unit":"","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"VL86Cx","unit":"","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv2","unit":"","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM2","unit":"","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MEMC","unit":"","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":2,"unit":"µm","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":27000,"unit":"","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":30.25,"unit":"mm²","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl2333&oldid=24890","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"","sourceId":"chipswiki-7634-r24890","location":"Vti/vl86cx/vl2333 · revision 24890 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-84&oldid=92366","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":29.41,"unit":"mm","sourceId":"chipswiki-31441-r92366","location":"Template:Packages/vti/plcc-84 · revision 92366 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-03b6871ece53d3bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-84&oldid=92366","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":30.35,"unit":"mm","sourceId":"chipswiki-31441-r92366","location":"Template:Packages/vti/plcc-84 · revision 92366 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ES–25KC\\W","unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ES–25KC\\W","unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ES","unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14624-r44685","location":"Amd/am186ex/am186es–25kc\\w · revision 44685 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-03f862c09fe5f229","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325kc%5Cw&oldid=44685","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14624-r44685"],"url":"https://museum.vlsi.kr/objects/cw-03f862c09fe5f229"},{"id":"cw-04095bb1637e9ebf","name":"VY86C06020","kind":"sku","entityType":"product-model","subtype":"soc","company":"Arm","year":1994,"architecture":"ARM6","process":"0.8 µm","aliases":["Vti vl86cx vy86c06020"],"fields":[{"key":"Model name","value":"VY86C06020","unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"VY86C06020","unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C06020FC","unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C06020FC-2","unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1994,"unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"VL86Cx","unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv3","unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM6","unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MEMC","unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM60","unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.8,"unit":"µm","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":35530,"unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":5.89,"unit":"mm²","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"","sourceId":"chipswiki-7631-r24886","location":"Vti/vl86cx/vy86c06020 · revision 24886 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c06020&oldid=24886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"MQFP-100","unit":"","sourceId":"chipswiki-31438-r92360","location":"Template:Packages/vti/mqfp-100 · revision 92360 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fmqfp-100&oldid=92360","sourceDate":"2017-07-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"MQFP","unit":"","sourceId":"chipswiki-31438-r92360","location":"Template:Packages/vti/mqfp-100 · revision 92360 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04095bb1637e9ebf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fmqfp-100&oldid=92360","sourceDate":"2017-07-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7631-r24886","chipswiki-31438-r92360"],"url":"https://museum.vlsi.kr/objects/cw-04095bb1637e9ebf"},{"id":"cw-040da7891ad11cd8","name":"CN5860-900 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5860-900bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN5860-900 NSP","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5860-900 NSP","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5860-900BG1521-NSP","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x16 KiB","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8115-r25774","location":"Cavium/octeon plus/cn5860-900bg1521-nsp · revision 25774 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-nsp&oldid=25774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-040da7891ad11cd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8115-r25774","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-040da7891ad11cd8"},{"id":"cw-041800e67faf9c61","name":"Embedded G-Series T48E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"G-Series APU/CPU","year":2012,"architecture":"Bobcat","process":"40 nm","aliases":["Amd embedded t48e"],"fields":[{"key":"Model name","value":"Embedded G-Series T48E","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"T48E","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GET48EGBB22GVE","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Embedded G-Series","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G-Series APU/CPU","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bobcat","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"eBrazos","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":20,"unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":451000000,"unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":75,"unit":"mm²","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2 × 512 KiB","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. 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Not an independent measurement.","entityId":"cw-041800e67faf9c61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft48e&oldid=891","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-419-r891","location":"Amd/embedded/t48e · revision 891 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. 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Not an independent measurement.","entityId":"cw-042349384f18f96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbd&oldid=951","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-400MBDBC","unit":"","sourceId":"chipswiki-470-r951","location":"Alchemy/au1100-400mbd · revision 951 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-042349384f18f96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbd&oldid=951","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-470-r951","location":"Alchemy/au1100-400mbd · revision 951 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-042349384f18f96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbd&oldid=951","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-470-r951","location":"Alchemy/au1100-400mbd · revision 951 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-042349384f18f96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbd&oldid=951","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-470-r951","location":"Alchemy/au1100-400mbd · revision 951 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-042349384f18f96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbd&oldid=951","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-470-r951","location":"Alchemy/au1100-400mbd · revision 951 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-042349384f18f96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbd&oldid=951","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.400 GB/s","unit":"","sourceId":"chipswiki-470-r951","location":"Alchemy/au1100-400mbd · revision 951 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-042349384f18f96d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-400mbd&oldid=951","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-470-r951"],"url":"https://museum.vlsi.kr/objects/cw-042349384f18f96d"},{"id":"cw-042ce3965b869a38","name":"K5","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":1996,"process":"500 nm","aliases":["Amd microarchitectures k5"],"fields":[{"key":"Architecture name","value":"K5","unit":"","sourceId":"chipswiki-8757-r27209","location":"Amd/microarchitectures/k5 · revision 27209 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-042ce3965b869a38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk5&oldid=27209","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8757-r27209","location":"Amd/microarchitectures/k5 · revision 27209 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-042ce3965b869a38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk5&oldid=27209","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8757-r27209","location":"Amd/microarchitectures/k5 · revision 27209 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-042ce3965b869a38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk5&oldid=27209","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"March 27, 1996","unit":"","sourceId":"chipswiki-8757-r27209","location":"Amd/microarchitectures/k5 · revision 27209 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-042ce3965b869a38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk5&oldid=27209","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8757-r27209","location":"Amd/microarchitectures/k5 · revision 27209 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-042ce3965b869a38","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk5&oldid=27209","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8757-r27209","location":"Amd/microarchitectures/k5 · revision 27209 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-01. 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Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701121801","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-7948-r25496","location":"Intel/core i5/i5-2547m · revision 25496 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2547m&oldid=25496","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-045757d249716d91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7948-r25496","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-045757d249716d91"},{"id":"cw-047b4378f81d5bf9","name":"N8086","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N8086","year":null,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 n8086"],"fields":[{"key":"Model name","value":"AMD N8086","unit":"","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N8086","unit":"","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"N8086","unit":"","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N8086","unit":"","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":5,"unit":"MHz","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-44","unit":"","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8499-r26692","location":"Amd/am8086/n8086 · revision 26692 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-047b4378f81d5bf9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086&oldid=26692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8499-r26692"],"url":"https://museum.vlsi.kr/objects/cw-047b4378f81d5bf9"},{"id":"cw-049ae2e936083e0a","name":"Xeon E7-8890 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E7-8000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e7 e7-8890 v4"],"fields":[{"key":"Model name","value":"Xeon E7-8890 v4","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-8890 v4","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-8000","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":3,"unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EX","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"3.07 TiB","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x256 KiB","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":60,"unit":"MiB","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"24x2.5 MiB","unit":"","sourceId":"chipswiki-6345-r19673","location":"Intel/xeon e7/e7-8890 v4 · revision 19673 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-01. Not an independent measurement.","entityId":"cw-049ae2e936083e0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8890%20v4&oldid=19673","sourceDate":"2018-05-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6345-r19673"],"url":"https://museum.vlsi.kr/objects/cw-049ae2e936083e0a"},{"id":"cw-04a37d60d8cdc8ce","name":"R-Car M3","kind":"sku","entityType":"product-model","subtype":"soc","company":"Renesas","series":"3rd Gen","year":2016,"architecture":"Cortex-A53","process":"16 nm","aliases":["Renesas r-car m3"],"fields":[{"key":"Model name","value":"R-Car M3","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Renesas","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"M3","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"R8A77960Frequency","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 19, 2016","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October, 2016","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"R-Car","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"3rd Gen","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A57","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-R7","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":7,"unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":7,"unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.9,"unit":"V","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x48+5x32 KiB","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":224,"unit":"KiB","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"7x32 KiB","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-3200","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR GX6250","unit":"","sourceId":"chipswiki-7644-r24904","location":"Renesas/r-car/m3 · revision 24904 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm3&oldid=24904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1022","unit":"","sourceId":"chipswiki-31421-r92285","location":"Template:Packages/renesas/fcbga-1022 · revision 92285 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1022&oldid=92285","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31421-r92285","location":"Template:Packages/renesas/fcbga-1022 · revision 92285 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1022&oldid=92285","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1022,"unit":"","sourceId":"chipswiki-31421-r92285","location":"Template:Packages/renesas/fcbga-1022 · revision 92285 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1022&oldid=92285","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31421-r92285","location":"Template:Packages/renesas/fcbga-1022 · revision 92285 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1022&oldid=92285","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":29,"unit":"mm","sourceId":"chipswiki-31421-r92285","location":"Template:Packages/renesas/fcbga-1022 · revision 92285 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1022&oldid=92285","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":29,"unit":"mm","sourceId":"chipswiki-31421-r92285","location":"Template:Packages/renesas/fcbga-1022 · revision 92285 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04a37d60d8cdc8ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1022&oldid=92285","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7644-r24904","chipswiki-31421-r92285"],"url":"https://museum.vlsi.kr/objects/cw-04a37d60d8cdc8ce"},{"id":"cw-04dc30e3e76dad1f","name":"Ryzen 9 5900HS","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 9 5900hs"],"fields":[{"key":"Model name","value":"Ryzen 9 5900HS","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5900HS","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000300","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 9","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4600,"unit":"MHz","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":2100,"unit":"MHz","sourceId":"chipswiki-721-r1731","location":"Amd/ryzen 9/5900hs · revision 1731 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-04dc30e3e76dad1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hs&oldid=1731","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-721-r1731"],"url":"https://museum.vlsi.kr/objects/cw-04dc30e3e76dad1f"},{"id":"cw-04e4b2257049b1ed","name":"Atom x3-C3445","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"C3000","year":2015,"architecture":"Silvermont","process":"28 nm","aliases":["Intel atom x3 x3-c3445"],"fields":[{"key":"Model name","value":"Atom x3-C3445","unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"x3-C3445","unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April, 2015","unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April, 2015","unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom x3","unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"C3000","unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Silvermont","unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"SoFIA","unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"SoFIA","unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-8046-r25682","location":"Intel/atom x3/x3-c3445 · revision 25682 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04e4b2257049b1ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3445&oldid=25682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8046-r25682"],"url":"https://museum.vlsi.kr/objects/cw-04e4b2257049b1ed"},{"id":"cw-04f1ac7d3a88f732","name":"Xeon E5-4610 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-4000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-4610 v4"],"fields":[{"key":"Model name","value":"Xeon E5-4610 v4","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-4610 v4","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-4000","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2.5,"unit":"MiB","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x256 KiB","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":25,"unit":"MiB","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x2.5 MiB","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7716-r25088","location":"Intel/xeon e5/e5-4610 v4 · revision 25088 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-04f1ac7d3a88f732","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4610%20v4&oldid=25088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7716-r25088"],"url":"https://museum.vlsi.kr/objects/cw-04f1ac7d3a88f732"},{"id":"cw-04ffe6cb8bdfc39d","name":"Core i7-7820HK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-7800","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i7 i7-7820hk"],"fields":[{"key":"Model name","value":"Core i7-7820HK","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-7820HK","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR32P","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-7800","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-6415-r20014","location":"Intel/core i7/i7-7820hk · revision 20014 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hk&oldid=20014","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-04ffe6cb8bdfc39d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6415-r20014","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-04ffe6cb8bdfc39d"},{"id":"cw-0510146154044c10","name":"Pentium B950","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"900","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel pentium (2009) b950"],"fields":[{"key":"Model name","value":"Pentium B950","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"B950","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700847901","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR07T","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 13, 2011","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 13, 2011","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":900,"unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-987-r2811","location":"Intel/pentium (2009)/b950 · revision 2811 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb950&oldid=2811","sourceDate":"2020-08-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-05. Not an independent measurement.","entityId":"cw-0510146154044c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-987-r2811","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-0510146154044c10"},{"id":"cw-0518c3bdfe447877","name":"3805","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Fairchild","year":1972,"aliases":["Fairchild pps-25 3805"],"fields":[{"key":"Model name","value":"PPS-25 3805","unit":"","sourceId":"chipswiki-8108-r25767","location":"Fairchild/pps-25/3805 · revision 25767 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0518c3bdfe447877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fairchild%2Fpps-25%2F3805&oldid=25767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Fairchild","unit":"","sourceId":"chipswiki-8108-r25767","location":"Fairchild/pps-25/3805 · revision 25767 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0518c3bdfe447877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fairchild%2Fpps-25%2F3805&oldid=25767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Fairchild","unit":"","sourceId":"chipswiki-8108-r25767","location":"Fairchild/pps-25/3805 · revision 25767 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0518c3bdfe447877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fairchild%2Fpps-25%2F3805&oldid=25767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3805,"unit":"","sourceId":"chipswiki-8108-r25767","location":"Fairchild/pps-25/3805 · revision 25767 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0518c3bdfe447877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fairchild%2Fpps-25%2F3805&oldid=25767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1971,"unit":"","sourceId":"chipswiki-8108-r25767","location":"Fairchild/pps-25/3805 · revision 25767 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0518c3bdfe447877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fairchild%2Fpps-25%2F3805&oldid=25767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"1972 or (2Q, 1971)","unit":"","sourceId":"chipswiki-8108-r25767","location":"Fairchild/pps-25/3805 · revision 25767 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0518c3bdfe447877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fairchild%2Fpps-25%2F3805&oldid=25767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"kHz","sourceId":"chipswiki-8108-r25767","location":"Fairchild/pps-25/3805 · revision 25767 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0518c3bdfe447877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fairchild%2Fpps-25%2F3805&oldid=25767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":4,"unit":"bit","sourceId":"chipswiki-8108-r25767","location":"Fairchild/pps-25/3805 · revision 25767 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0518c3bdfe447877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fairchild%2Fpps-25%2F3805&oldid=25767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8108-r25767","location":"Fairchild/pps-25/3805 · revision 25767 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0518c3bdfe447877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Fairchild%2Fpps-25%2F3805&oldid=25767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8108-r25767"],"url":"https://museum.vlsi.kr/objects/cw-0518c3bdfe447877"},{"id":"cw-051a94ffa399938b","name":"Xeon E-2234","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2200","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2234"],"fields":[{"key":"Model name","value":"Xeon E-2234","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2234","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068404174806","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFAX","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2200","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4800,"unit":"MHz","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake ER","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":71,"unit":"W","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-1243-r3964","location":"Intel/xeon e/e-2234 · revision 3964 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-051a94ffa399938b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2234&oldid=3964","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1243-r3964"],"url":"https://museum.vlsi.kr/objects/cw-051a94ffa399938b"},{"id":"cw-055507867c729b38","name":"N80L286-8","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N80L286","year":1989,"architecture":"80286","aliases":["Amd am286 n80l286-8"],"fields":[{"key":"Model name","value":"N80L286-8","unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N80L286-8","unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"N80L286-8","unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1989,"unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N80L286","unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"8 MT/s","unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":134000,"unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":73,"unit":"mm²","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-68","unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PLCC-68","unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8586-r26784","location":"Amd/am286/n80l286-8 · revision 26784 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-055507867c729b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-8&oldid=26784","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8586-r26784"],"url":"https://museum.vlsi.kr/objects/cw-055507867c729b38"},{"id":"cw-05a2f4d7a5ac85a8","name":"Xeon E5-2648L v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2648l v4"],"fields":[{"key":"Model name","value":"Xeon E5-2648L v4","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2648L v4","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002189001","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2ND","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4700000000,"unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":306.18,"unit":"mm²","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":14,"unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":28,"unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":75,"unit":"W","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":448,"unit":"KiB","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":448,"unit":"KiB","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3.5,"unit":"MiB","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x256 KiB","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35,"unit":"MiB","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x2.5 MiB","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7736-r25113","location":"Intel/xeon e5/e5-2648l v4 · revision 25113 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05a2f4d7a5ac85a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2648l%20v4&oldid=25113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7736-r25113"],"url":"https://museum.vlsi.kr/objects/cw-05a2f4d7a5ac85a8"},{"id":"cw-05a6dbfb910b47ad","name":"EPYC 7643","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 7643"],"fields":[{"key":"Model name","value":"EPYC 7643","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7643,"unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000326","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000326WOF","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":48,"unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":96,"unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":225,"unit":"W","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":3,"unit":"MiB","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1536,"unit":"KiB","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"48 × 32 KiB","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1536,"unit":"KiB","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"48 × 32 KiB","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"48 × 512 KiB","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8 × 32 MiB","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-736-r1757","location":"Amd/epyc/7643 · revision 1757 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-05a6dbfb910b47ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7643&oldid=1757","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-736-r1757"],"url":"https://museum.vlsi.kr/objects/cw-05a6dbfb910b47ad"},{"id":"cw-05c8fea0f13698fa","name":"CN3840-400 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3840-400bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3840-400 NSP","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3840-400 NSP","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3840-400BG1521-NSP","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x8 KiB","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8219-r25878","location":"Cavium/octeon/cn3840-400bg1521-nsp · revision 25878 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-nsp&oldid=25878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-05c8fea0f13698fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8219-r25878","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-05c8fea0f13698fa"},{"id":"cw-06074bc35cf5c3f2","name":"Am486SE-25","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486SE","year":null,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486se-25"],"fields":[{"key":"Model name","value":"Am486SE-25","unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486SE-25","unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am486SE-25","unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486SE","unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"25 MT/s","unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SX","unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":900000,"unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8541-r26737","location":"Amd/am486/am486se-25 · revision 26737 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06074bc35cf5c3f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486se-25&oldid=26737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8541-r26737"],"url":"https://museum.vlsi.kr/objects/cw-06074bc35cf5c3f2"},{"id":"cw-0626e5409d9da68d","name":"Core i5-9400T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-9000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i5 i5-9400t"],"fields":[{"key":"Model name","value":"Core i5-9400T","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-9400T","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403358915","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3X8","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-9000","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake R","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-2841-r9525","location":"Intel/core i5/i5-9400t · revision 9525 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-0626e5409d9da68d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2841-r9525"],"url":"https://museum.vlsi.kr/objects/cw-0626e5409d9da68d"},{"id":"cw-0678fc2061510a35","name":"CN3850-400 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3850-400bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN3850-400 EXP","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3850-400 EXP","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3850-400BG1521-EXP","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x8 KiB","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8211-r25870","location":"Cavium/octeon/cn3850-400bg1521-exp · revision 25870 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-exp&oldid=25870","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0678fc2061510a35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8211-r25870","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-0678fc2061510a35"},{"id":"cw-0680a04eba3161b4","name":"J80186-6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1984,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 j80186-6"],"fields":[{"key":"Model name","value":"J80186-6","unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J80186-6","unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"J80186-6","unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"J80186-6B","unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":6,"unit":"MHz","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"1.5 MT/s","unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-68","unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PLCC-68","unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8637-r26836","location":"Amd/am186/j80186-6 · revision 26836 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0680a04eba3161b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-6&oldid=26836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8637-r26836"],"url":"https://museum.vlsi.kr/objects/cw-0680a04eba3161b4"},{"id":"cw-06822549accccb8c","name":"Ryzen 7 2700X Gold Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 7 2700x gold edition"],"fields":[{"key":"Model name","value":"Ryzen 7 2700X Gold Edition","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2700X Gold Edition","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD270XBGAFA50","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 29, 2019","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 29, 2019","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2000,"unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3700,"unit":"MHz","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Pinnacle Ridge","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x64 KiB","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x8 MiB","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-2932-r9799","location":"Amd/ryzen 7/2700x gold edition · revision 9799 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700x%20gold%20edition&oldid=9799","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-06822549accccb8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2932-r9799","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-06822549accccb8c"},{"id":"cw-069992c55d73bc28","name":"Core i5-560UM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-500","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i5 i5-560um"],"fields":[{"key":"Model name","value":"Intel Core i5-560UM","unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-560UM","unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617005190AH","unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 26, 2010","unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 26, 2010","unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-500","unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1333.33,"unit":"MHz","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2133.33,"unit":"MHz","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBSN","unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-069992c55d73bc28","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-560um&oldid=25475","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7932-r25475","location":"Intel/core i5/i5-560um · revision 25475 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x8 KiB","unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8208-r25867","location":"Cavium/octeon/cn3850-500bg1521-exp · revision 25867 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-exp&oldid=25867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06aa45c92aa79ff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8208-r25867","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-06aa45c92aa79ff3"},{"id":"cw-06ea5783d339e5f6","name":"Core i7-6822EQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-6822eq"],"fields":[{"key":"Model name","value":"Core i7-6822EQ","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6822EQ","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8066202302204","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2DW","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 12, 2015","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 12, 2015","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7835-r25326","location":"Intel/core i7/i7-6822eq · revision 25326 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6822eq&oldid=25326","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-06ea5783d339e5f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7835-r25326","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-06ea5783d339e5f6"},{"id":"cw-0711b372e80bb97b","name":"Xeon D-1623N","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1600","year":2019,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1623n"],"fields":[{"key":"Model name","value":"Xeon D-1623N","unit":"","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. 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Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1623N","unit":"","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. 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Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. 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Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. 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Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. 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Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. 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Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-0711b372e80bb97b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1623n&oldid=11014","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-3686-r11014","location":"Intel/xeon d/d-1623n · revision 11014 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. 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Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1500","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics P630","unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6410-r20009","location":"Intel/xeon e3/e3-1505l v6 · revision 20009 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505l%20v6&oldid=20009","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-075f51022b02d439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6410-r20009","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-075f51022b02d439"},{"id":"cw-0761c6447d36769c","name":"Pentium G4600T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"G4600","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel pentium (2009) g4600t"],"fields":[{"key":"Model name","value":"Pentium G4600T","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4600T","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8067703016014","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR35R","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G4600","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":92,"unit":"°C","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-7782-r25217","location":"Intel/pentium (2009)/g4600t · revision 25217 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0761c6447d36769c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4600t&oldid=25217","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7782-r25217"],"url":"https://museum.vlsi.kr/objects/cw-0761c6447d36769c"},{"id":"cw-0765d7280670c171","name":"Core","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2006,"process":"65 nm","aliases":["Intel microarchitectures core (client)"],"fields":[{"key":"Architecture name","value":"Core","unit":"","sourceId":"chipswiki-6981-r21821","location":"Intel/microarchitectures/core (client) · revision 21821 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-0765d7280670c171","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcore%20(client)&oldid=21821","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6981-r21821","location":"Intel/microarchitectures/core (client) · revision 21821 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-0765d7280670c171","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcore%20(client)&oldid=21821","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6981-r21821","location":"Intel/microarchitectures/core (client) · revision 21821 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-0765d7280670c171","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcore%20(client)&oldid=21821","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"April, 2006","unit":"","sourceId":"chipswiki-6981-r21821","location":"Intel/microarchitectures/core (client) · revision 21821 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-0765d7280670c171","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcore%20(client)&oldid=21821","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6981-r21821","location":"Intel/microarchitectures/core (client) · revision 21821 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-0765d7280670c171","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcore%20(client)&oldid=21821","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-6981-r21821","location":"Intel/microarchitectures/core (client) · revision 21821 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-0765d7280670c171","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcore%20(client)&oldid=21821","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Modified Pentium M","unit":"","sourceId":"chipswiki-6981-r21821","location":"Intel/microarchitectures/core (client) · revision 21821 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-0765d7280670c171","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcore%20(client)&oldid=21821","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Penryn","unit":"","sourceId":"chipswiki-6981-r21821","location":"Intel/microarchitectures/core (client) · revision 21821 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-0765d7280670c171","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcore%20(client)&oldid=21821","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6981-r21821"],"url":"https://museum.vlsi.kr/objects/cw-0765d7280670c171"},{"id":"cw-07738bcd895815f5","name":"Ryzen Threadripper PRO 3945WX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3900","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen threadripper pro 3945wx"],"fields":[{"key":"Model name","value":"Ryzen Threadripper PRO 3945WX","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 3945WX","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000168","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 14, 2020","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Threadripper","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3900,"unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":4000,"unit":"MHz","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"WRX80","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Castle Peak","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":15940000000,"unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":280,"unit":"W","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12 × 32 KiB","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12 × 32 KiB","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12 × 512 KiB","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 16 MiB","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"204.8 GB/s","unit":"","sourceId":"chipswiki-387-r832","location":"Amd/ryzen threadripper/pro 3945wx · revision 832 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203945wx&oldid=832","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OLGA","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.87,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":75.4,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":58.5,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":6.26,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-07738bcd895815f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-387-r832","chipswiki-31095-r91554"],"url":"https://museum.vlsi.kr/objects/cw-07738bcd895815f5"},{"id":"cw-078a73ea718a172e","name":"Ryzen 7 5700GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 7 5700ge"],"fields":[{"key":"Model name","value":"Ryzen 7 5700GE","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5700GE","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000260","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 13, 2021","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4600,"unit":"MHz","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":2000,"unit":"MHz","sourceId":"chipswiki-718-r1726","location":"Amd/ryzen 7/5700ge · revision 1726 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-078a73ea718a172e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700ge&oldid=1726","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-718-r1726"],"url":"https://museum.vlsi.kr/objects/cw-078a73ea718a172e"},{"id":"cw-082af1423456f430","name":"Exynos M5","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Samsung","year":2020,"process":"7 nm","aliases":["Samsung microarchitectures m5"],"fields":[{"key":"Architecture name","value":"Lion M5","unit":"","sourceId":"chipswiki-660-r1596","location":"Samsung/microarchitectures/m5 · revision 1596 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-082af1423456f430","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm5&oldid=1596","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-660-r1596","location":"Samsung/microarchitectures/m5 · revision 1596 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-082af1423456f430","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm5&oldid=1596","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-660-r1596","location":"Samsung/microarchitectures/m5 · revision 1596 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-082af1423456f430","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm5&oldid=1596","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2020,"unit":"","sourceId":"chipswiki-660-r1596","location":"Samsung/microarchitectures/m5 · revision 1596 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-082af1423456f430","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm5&oldid=1596","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-660-r1596","location":"Samsung/microarchitectures/m5 · revision 1596 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-082af1423456f430","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm5&oldid=1596","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-660-r1596","location":"Samsung/microarchitectures/m5 · revision 1596 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-082af1423456f430","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm5&oldid=1596","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-660-r1596","location":"Samsung/microarchitectures/m5 · revision 1596 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-082af1423456f430","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm5&oldid=1596","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-660-r1596","location":"Samsung/microarchitectures/m5 · revision 1596 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-082af1423456f430","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm5&oldid=1596","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":16,"unit":"","sourceId":"chipswiki-660-r1596","location":"Samsung/microarchitectures/m5 · revision 1596 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-082af1423456f430","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm5&oldid=1596","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"6-way","unit":"","sourceId":"chipswiki-660-r1596","location":"Samsung/microarchitectures/m5 · revision 1596 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-082af1423456f430","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm5&oldid=1596","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-660-r1596","location":"Samsung/microarchitectures/m5 · revision 1596 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-082af1423456f430","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm5&oldid=1596","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-660-r1596","location":"Samsung/microarchitectures/m5 · revision 1596 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-082af1423456f430","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm5&oldid=1596","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-660-r1596","location":"Samsung/microarchitectures/m5 · revision 1596 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"cluster","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-082af1423456f430","scope":"cluster","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm5&oldid=1596","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"M4","unit":"","sourceId":"chipswiki-660-r1596","location":"Samsung/microarchitectures/m5 · revision 1596 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-28. Not an independent measurement.","entityId":"cw-082af1423456f430","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm5&oldid=1596","sourceDate":"2021-07-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-660-r1596"],"url":"https://museum.vlsi.kr/objects/cw-082af1423456f430"},{"id":"cw-082bbe1582c9616e","name":"Celeron G4900","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel celeron g4900"],"fields":[{"key":"Model name","value":"Celeron G4900","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4900","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80684G4900","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80684G4900","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403378112","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3W4","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":54,"unit":"W","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 610","unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-6448-r20183","location":"Intel/celeron/g4900 · revision 20183 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-082bbe1582c9616e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900&oldid=20183","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6448-r20183"],"url":"https://museum.vlsi.kr/objects/cw-082bbe1582c9616e"},{"id":"cw-083990cd23c8ddba","name":"ThunderX2 CN9970","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","year":2018,"architecture":"Vulcan","process":"16 nm","aliases":["Cavium thunderx2 cn9970"],"fields":[{"key":"Model name","value":"ThunderX2 CN9970","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN9970","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9970-2500LG4077-Y21-G","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9970-2400LG4077-Y21-G","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9970-2300LG4077-Y21-G","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9970-2200LG4077-Y21-G","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9970-2100LG4077-Y21-G","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9970-2000LG4077-Y21-G","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / part number 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 6","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"part number 6","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9970-1800LG4077-Y21-G","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / part number 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 7","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"part number 7","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 7, 2018","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 7, 2018","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"ThunderX2","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1800,"unit":"MHz","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2000,"unit":"MHz","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":2100,"unit":"MHz","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 4","value":2200,"unit":"MHz","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / frequency 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 4","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"Multiple clock domains; raw parameter frequency 4","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 5","value":2300,"unit":"MHz","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / frequency 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 5","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"Multiple clock domains; raw parameter frequency 5","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 6","value":2400,"unit":"MHz","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / frequency 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 6","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"Multiple clock domains; raw parameter frequency 6","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 7","value":2500,"unit":"MHz","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / frequency 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 7","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"Multiple clock domains; raw parameter frequency 7","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.1","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Vulcan","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":96,"unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x256 KiB","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24,"unit":"MiB","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-4333-r13946","location":"Cavium/thunderx2/cn9970 · revision 13946 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-083990cd23c8ddba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4333-r13946"],"url":"https://museum.vlsi.kr/objects/cw-083990cd23c8ddba"},{"id":"cw-083bd70b21971c10","name":"8086/BQA","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"M8086","year":null,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 8086-bqa"],"fields":[{"key":"Model name","value":"8086/BQA","unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8086/BQA","unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"8086/BQA","unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Military","unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"M8086","unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":5,"unit":"MHz","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8519-r26712","location":"Amd/am8086/8086-bqa · revision 26712 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-083bd70b21971c10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2F8086-bqa&oldid=26712","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8519-r26712"],"url":"https://museum.vlsi.kr/objects/cw-083bd70b21971c10"},{"id":"cw-08543040c10e9407","name":"Cortex-A710","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2021,"process":"7 nm","aliases":["Arm holdings microarchitectures cortex-a710"],"fields":[{"key":"Architecture name","value":"Cortex-A710","unit":"","sourceId":"chipswiki-311-r627","location":"Arm holdings/microarchitectures/cortex-a710 · revision 627 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-08543040c10e9407","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a710&oldid=627","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-311-r627","location":"Arm holdings/microarchitectures/cortex-a710 · revision 627 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-08543040c10e9407","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a710&oldid=627","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-311-r627","location":"Arm holdings/microarchitectures/cortex-a710 · revision 627 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-08543040c10e9407","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a710&oldid=627","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2021,"unit":"","sourceId":"chipswiki-311-r627","location":"Arm holdings/microarchitectures/cortex-a710 · revision 627 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-08543040c10e9407","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a710&oldid=627","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-311-r627","location":"Arm holdings/microarchitectures/cortex-a710 · revision 627 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-08543040c10e9407","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a710&oldid=627","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":5,"unit":"nm","sourceId":"chipswiki-311-r627","location":"Arm holdings/microarchitectures/cortex-a710 · revision 627 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-08543040c10e9407","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a710&oldid=627","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-311-r627","location":"Arm holdings/microarchitectures/cortex-a710 · revision 627 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-08543040c10e9407","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a710&oldid=627","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A78","unit":"","sourceId":"chipswiki-311-r627","location":"Arm holdings/microarchitectures/cortex-a710 · revision 627 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-08543040c10e9407","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a710&oldid=627","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A715","unit":"","sourceId":"chipswiki-311-r627","location":"Arm holdings/microarchitectures/cortex-a710 · revision 627 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-08543040c10e9407","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a710&oldid=627","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-311-r627"],"url":"https://museum.vlsi.kr/objects/cw-08543040c10e9407"},{"id":"cw-086595701a5aa9d6","name":"Duron 1800 (Applebred)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2003,"architecture":"K7","process":"130 nm","aliases":["Amd duron dhd1800dlv1c"],"fields":[{"key":"Model name","value":"Duron 1800","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 1800","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHD1800DLV1C","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2003","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2003","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266.66 MT/s","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Applebred","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37200000,"unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":80.89,"unit":"mm²","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":57,"unit":"W","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-086595701a5aa9d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1800dlv1c&oldid=26130","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8422-r26130","location":"Amd/duron/dhd1800dlv1c · revision 26130 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3830-400 SCP","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8227-r25886","location":"Cavium/octeon/cn3830-400bg1521-scp · revision 25886 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-scp&oldid=25886","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08660d3dba8f4a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8227-r25886","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-08660d3dba8f4a02"},{"id":"cw-0891fcf5bcdc18bc","name":"i486SL-33","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486SL","year":1992,"architecture":"80486","process":"800 nm","aliases":["Intel 80486 486sl-33"],"fields":[{"key":"Model name","value":"Intel i486SL-33","unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486SL-33","unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KU80486SL-33","unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 9, 1992","unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486SL","unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX746","unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX805","unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SL","unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1400000,"unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8082-r25733","location":"Intel/80486/486sl-33 · revision 25733 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0891fcf5bcdc18bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sl-33&oldid=25733","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8082-r25733"],"url":"https://museum.vlsi.kr/objects/cw-0891fcf5bcdc18bc"},{"id":"cw-08bd6a3572119811","name":"Neoverse V1","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2021,"process":"7 nm","aliases":["Arm holdings microarchitectures neoverse v1"],"fields":[{"key":"Architecture name","value":"Neoverse V1","unit":"","sourceId":"chipswiki-298-r602","location":"Arm holdings/microarchitectures/neoverse v1 · revision 602 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-08bd6a3572119811","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20v1&oldid=602","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-298-r602","location":"Arm holdings/microarchitectures/neoverse v1 · revision 602 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-08bd6a3572119811","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20v1&oldid=602","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-298-r602","location":"Arm holdings/microarchitectures/neoverse v1 · revision 602 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-08bd6a3572119811","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20v1&oldid=602","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2021,"unit":"","sourceId":"chipswiki-298-r602","location":"Arm holdings/microarchitectures/neoverse v1 · revision 602 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-08bd6a3572119811","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20v1&oldid=602","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-298-r602","location":"Arm holdings/microarchitectures/neoverse v1 · revision 602 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-08bd6a3572119811","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20v1&oldid=602","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Neoverse N1","unit":"","sourceId":"chipswiki-298-r602","location":"Arm holdings/microarchitectures/neoverse v1 · revision 602 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-08bd6a3572119811","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fneoverse%20v1&oldid=602","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-298-r602"],"url":"https://museum.vlsi.kr/objects/cw-08bd6a3572119811"},{"id":"cw-08c00fda253e2908","name":"CN5830-600 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5830-600bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN5830-600 SCP","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5830-600 SCP","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5830-600BG1521-SCP","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x16 KiB","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8156-r25815","location":"Cavium/octeon plus/cn5830-600bg1521-scp · revision 25815 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-scp&oldid=25815","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08c00fda253e2908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8156-r25815","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-08c00fda253e2908"},{"id":"cw-08e956e4c2d3a663","name":"CN5734-800 SP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5734-800bg1217-sp"],"fields":[{"key":"Model name","value":"Cavium CN5734-800 SP","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5734-800 SP","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5734-800BG1217-SP","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":288,"unit":"KiB","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x16 KiB","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8189-r25848","location":"Cavium/octeon plus/cn5734-800bg1217-sp · revision 25848 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-sp&oldid=25848","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08e956e4c2d3a663","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8189-r25848","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-08e956e4c2d3a663"},{"id":"cw-08ed8b6a2a9fc453","name":"ID8086-2B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"ID8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 id8086-2b"],"fields":[{"key":"Model name","value":"AMD ID8086-2B","unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"ID8086-2B","unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"ID8086-2B","unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"ID8086","unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8510-r26703","location":"Amd/am8086/id8086-2b · revision 26703 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-08ed8b6a2a9fc453","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086-2b&oldid=26703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8510-r26703"],"url":"https://museum.vlsi.kr/objects/cw-08ed8b6a2a9fc453"},{"id":"cw-08f46df84c2e2e91","name":"Exynos 8895","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 9","year":2017,"architecture":"Mongoose 2","process":"10 nm","aliases":["Samsung exynos 8895"],"fields":[{"key":"Model name","value":"Exynos 8895","unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8895,"unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 23, 2017","unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"Mar 29, 2017","unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 9","unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2810,"unit":"MHz","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1840,"unit":"MHz","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Mongoose 2","unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Exynos M2","unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":103.64,"unit":"mm²","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-512-r1032","location":"Samsung/exynos/8895 · revision 1032 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-14. Not an independent measurement.","entityId":"cw-08f46df84c2e2e91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8895&oldid=1032","sourceDate":"2022-02-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-512-r1032"],"url":"https://museum.vlsi.kr/objects/cw-08f46df84c2e2e91"},{"id":"cw-090220f8351f0541","name":"Athlon MP 2100+","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2002,"architecture":"K7","process":"180 nm","aliases":["Amd athlon mp amp2100dms3c"],"fields":[{"key":"Model name","value":"AMD Athlon MP 2100+","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 2100+","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMP2100DMS3C","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 19, 2002","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 19, 2002","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1733,"unit":"MHz","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Palomino","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37500000,"unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":128,"unit":"mm²","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.75,"unit":"V","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":66,"unit":"W","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8453-r26646","location":"Amd/athlon mp/amp2100dms3c · revision 26646 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2100dms3c&oldid=26646","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OPGA-453","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"OPGA","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":453,"unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.942,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-090220f8351f0541","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8453-r26646","chipswiki-31459-r92404"],"url":"https://museum.vlsi.kr/objects/cw-090220f8351f0541"},{"id":"cw-0914884a37915983","name":"Alchemy Au1250-400MGF","kind":"sku","entityType":"product-model","subtype":"cpu","company":"RMI","year":2007,"architecture":"Au1","aliases":["Alchemy au1250-400mgf"],"fields":[{"key":"Model name","value":"Alchemy Au1250-400MGF","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"RMI","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1250-400MGF","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1250-400MGF","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 9, 2007","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 5, 2007","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.600 GB/s","unit":"","sourceId":"chipswiki-444-r925","location":"Alchemy/au1250-400mgf · revision 925 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0914884a37915983","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgf&oldid=925","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-444-r925"],"url":"https://museum.vlsi.kr/objects/cw-0914884a37915983"},{"id":"cw-09162d1d7a7d6919","name":"POWER7","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2010,"process":"45 nm","aliases":["Ibm microarchitectures power7"],"fields":[{"key":"Architecture name","value":"POWER7","unit":"","sourceId":"chipswiki-9920-r31544","location":"Ibm/microarchitectures/power7 · revision 31544 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. 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Not an independent measurement.","entityId":"cw-09162d1d7a7d6919","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower7&oldid=31544","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-9920-r31544","location":"Ibm/microarchitectures/power7 · revision 31544 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-09162d1d7a7d6919","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower7&oldid=31544","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2010,"unit":"","sourceId":"chipswiki-9920-r31544","location":"Ibm/microarchitectures/power7 · revision 31544 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-09162d1d7a7d6919","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower7&oldid=31544","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-9920-r31544","location":"Ibm/microarchitectures/power7 · revision 31544 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-09162d1d7a7d6919","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower7&oldid=31544","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-9920-r31544","location":"Ibm/microarchitectures/power7 · revision 31544 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. 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Not an independent measurement.","entityId":"cw-09162d1d7a7d6919","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower7&oldid=31544","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"POWER7+","unit":"","sourceId":"chipswiki-9920-r31544","location":"Ibm/microarchitectures/power7 · revision 31544 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-09162d1d7a7d6919","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower7&oldid=31544","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-9920-r31544"],"url":"https://museum.vlsi.kr/objects/cw-09162d1d7a7d6919"},{"id":"cw-091f1a011ef26539","name":"Core i3-7101E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7100","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7101e"],"fields":[{"key":"Model name","value":"Core i3-7101E","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8067702867060","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR32Z","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7100","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3900,"unit":"MHz","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":54,"unit":"W","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 610","unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7973-r25547","location":"Intel/core i3/i3-7101e · revision 25547 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-091f1a011ef26539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7101e&oldid=25547","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7973-r25547"],"url":"https://museum.vlsi.kr/objects/cw-091f1a011ef26539"},{"id":"cw-092b36dc51bd399d","name":"Kirin 970","kind":"sku","entityType":"product-model","subtype":"soc","company":"HiSilicon","series":"900","year":2017,"architecture":"Cortex-A53","process":"10 nm","aliases":["Hisilicon kirin 970"],"fields":[{"key":"Model name","value":"Kirin 970","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"HiSilicon","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":970,"unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Hi3670","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2017","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 1, 2017","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Kirin","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":900,"unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1800,"unit":"MHz","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2360,"unit":"MHz","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A73","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":5500000000,"unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":96.72,"unit":"mm²","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":512,"unit":"KiB","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":2,"unit":"MiB","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"1x2 MiB","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":256,"unit":"KiB","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 2)","value":"4x32 KiB","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 2)","value":"4x32 KiB","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":1,"unit":"MiB","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"1x1 MiB","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3732","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.82,"unit":"GiB/s","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G72","unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":746,"unit":"MHz","sourceId":"chipswiki-550-r1138","location":"Hisilicon/kirin/970 · revision 1138 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-01. Not an independent measurement.","entityId":"cw-092b36dc51bd399d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F970&oldid=1138","sourceDate":"2022-01-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-550-r1138"],"url":"https://museum.vlsi.kr/objects/cw-092b36dc51bd399d"},{"id":"cw-092d5816fa42aeef","name":"KaisHeng KH-25800","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Zhaoxin","series":"KH-20000","year":2017,"architecture":"WuDaoKou","process":"28 nm","aliases":["Zhaoxin kaisheng kh-25800"],"fields":[{"key":"Model name","value":"KaisHeng KH-25800","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Zhaoxin","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"HLMC","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"KH-25800","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KH-25800","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 28, 2017","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 28, 2017","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"KaisHeng","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"KH-20000","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"WuDaoKou","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2100000000,"unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":187,"unit":"mm²","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"32-way set associative","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7266-r23219","location":"Zhaoxin/kaisheng/kh-25800 · revision 23219 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-31. Not an independent measurement.","entityId":"cw-092d5816fa42aeef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaisheng%2Fkh-25800&oldid=23219","sourceDate":"2018-01-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7266-r23219"],"url":"https://museum.vlsi.kr/objects/cw-092d5816fa42aeef"},{"id":"cw-0938214d24f9560a","name":"CN5750-900 SSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5750-900bg1217-ssp"],"fields":[{"key":"Model name","value":"Cavium CN5750-900 SSP","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5750-900 SSP","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5750-900BG1217-SSP","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8162-r25821","location":"Cavium/octeon plus/cn5750-900bg1217-ssp · revision 25821 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-900bg1217-ssp&oldid=25821","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0938214d24f9560a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8162-r25821","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-0938214d24f9560a"},{"id":"cw-094c275368842dc5","name":"Ryzen 3 5300U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 3 5300u"],"fields":[{"key":"Model name","value":"Ryzen 3 5300U","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5300U","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000376","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Lucienne","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":104,"unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1500,"unit":"MHz","sourceId":"chipswiki-709-r1715","location":"Amd/ryzen 3/5300u · revision 1715 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-094c275368842dc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300u&oldid=1715","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-709-r1715"],"url":"https://museum.vlsi.kr/objects/cw-094c275368842dc5"},{"id":"cw-0953d80bbd5dcbcc","name":"CN5860-600 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5860-600bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN5860-600 EXP","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5860-600 EXP","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5860-600BG1521-EXP","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x16 KiB","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8122-r25781","location":"Cavium/octeon plus/cn5860-600bg1521-exp · revision 25781 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-exp&oldid=25781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0953d80bbd5dcbcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8122-r25781","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-0953d80bbd5dcbcc"},{"id":"cw-0975c30405b4cd42","name":"Godson-2C","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Loongson","series":"Godson 2","year":2004,"architecture":"GS464","process":"180 nm","aliases":["Loongson godson 2 2c"],"fields":[{"key":"Model name","value":"Godson-2C","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Loongson","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"SMICS","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2C","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DXP100","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2004,"unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 28, 2004","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Godson 2","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Godson 2","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"GS464","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"GS464","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":13500000,"unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":41.54,"unit":"mm²","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7683-r24978","location":"Loongson/godson 2/2c · revision 24978 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0975c30405b4cd42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2c&oldid=24978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7683-r24978"],"url":"https://museum.vlsi.kr/objects/cw-0975c30405b4cd42"},{"id":"cw-098a6a88f0ca239b","name":"Cortex-A7","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2011,"process":"40 nm","aliases":["Arm holdings microarchitectures cortex-a7"],"fields":[{"key":"Architecture name","value":"Cortex-A7","unit":"","sourceId":"chipswiki-4151-r13228","location":"Arm holdings/microarchitectures/cortex-a7 · revision 13228 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-098a6a88f0ca239b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a7&oldid=13228","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-4151-r13228","location":"Arm holdings/microarchitectures/cortex-a7 · revision 13228 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-098a6a88f0ca239b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a7&oldid=13228","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4151-r13228","location":"Arm holdings/microarchitectures/cortex-a7 · revision 13228 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-098a6a88f0ca239b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a7&oldid=13228","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"October 19, 2011","unit":"","sourceId":"chipswiki-4151-r13228","location":"Arm holdings/microarchitectures/cortex-a7 · revision 13228 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-098a6a88f0ca239b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a7&oldid=13228","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-4151-r13228","location":"Arm holdings/microarchitectures/cortex-a7 · revision 13228 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-098a6a88f0ca239b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a7&oldid=13228","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-4151-r13228","location":"Arm holdings/microarchitectures/cortex-a7 · revision 13228 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-098a6a88f0ca239b","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a7&oldid=13228","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-4151-r13228","location":"Arm holdings/microarchitectures/cortex-a7 · revision 13228 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-098a6a88f0ca239b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a7&oldid=13228","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A9","unit":"","sourceId":"chipswiki-4151-r13228","location":"Arm holdings/microarchitectures/cortex-a7 · revision 13228 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-098a6a88f0ca239b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a7&oldid=13228","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A53","unit":"","sourceId":"chipswiki-4151-r13228","location":"Arm holdings/microarchitectures/cortex-a7 · revision 13228 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-098a6a88f0ca239b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a7&oldid=13228","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4151-r13228"],"url":"https://museum.vlsi.kr/objects/cw-098a6a88f0ca239b"},{"id":"cw-09afe04791fff6b9","name":"Myriad 1 MA1102","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Movidius","series":"1","year":2010,"architecture":"LEON3","process":"65 nm","aliases":["Movidius myriad ma1102"],"fields":[{"key":"Model name","value":"Myriad 1 MA1102","unit":"","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Movidius","unit":"","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MA1102","unit":"","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2009,"unit":"","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2010,"unit":"","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Myriad","unit":"","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":1,"unit":"","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":180,"unit":"MHz","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"SPARC V8","unit":"","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"LEON3","unit":"","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"TSMC","unit":"","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":9,"unit":"","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":9,"unit":"","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-6953-r21695","location":"Movidius/myriad/ma1102 · revision 21695 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-13. Not an independent measurement.","entityId":"cw-09afe04791fff6b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1102&oldid=21695","sourceDate":"2018-03-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6953-r21695"],"url":"https://museum.vlsi.kr/objects/cw-09afe04791fff6b9"},{"id":"cw-0a419153315891b9","name":"Alchemy Au1200-500MGC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2005,"architecture":"Au1","aliases":["Alchemy au1200-500mgc"],"fields":[{"key":"Model name","value":"Alchemy Au1200-500MGC","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1200-500MGC","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1200-500MGC","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2005","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 2005","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"MiB","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1600 mW","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"2 GB/s","unit":"","sourceId":"chipswiki-452-r933","location":"Alchemy/au1200-500mgc · revision 933 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-0a419153315891b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-452-r933"],"url":"https://museum.vlsi.kr/objects/cw-0a419153315891b9"},{"id":"cw-0a4873decf40cd6b","name":"POWER9 02CY416","kind":"sku","entityType":"product-model","subtype":"cpu","company":"IBM","series":"POWER9","year":2017,"architecture":"POWER9","process":"14 nm","aliases":["Ibm power 02cy416"],"fields":[{"key":"Model name","value":"02CY416","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"02CY416","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"02CY416","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2017","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2017","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"POWER","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"POWER9","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.25,"unit":"GHz","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3.8,"unit":"GHz","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v3.0B","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"POWER9","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sforza","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8000000000,"unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":693.37,"unit":"mm²","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":72,"unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":85,"unit":"°C","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4.5,"unit":"MiB","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"9x512 KiB","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":90,"unit":"MiB","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"9x10 MiB","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-3942-r12572","location":"Ibm/power/02cy416 · revision 12572 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-0a4873decf40cd6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy416&oldid=12572","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3942-r12572"],"url":"https://museum.vlsi.kr/objects/cw-0a4873decf40cd6b"},{"id":"cw-0a83122678508068","name":"Helio P22","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio P","year":2018,"architecture":"Cortex-A53","process":"12 nm","aliases":["Mediatek helio p22"],"fields":[{"key":"Model name","value":"Helio P22","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P22","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 22, 2018","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 22, 2018","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio P","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":6,"unit":"GiB","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3200","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR GE8320","unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-789-r1949","location":"Mediatek/helio/p22 · revision 1949 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-19. Not an independent measurement.","entityId":"cw-0a83122678508068","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp22&oldid=1949","sourceDate":"2021-04-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-789-r1949"],"url":"https://museum.vlsi.kr/objects/cw-0a83122678508068"},{"id":"cw-0a89fa287f60903d","name":"UltraSPARC-I 143MHz","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Sun Microsystems","series":"UltraSPARC-I","year":1995,"architecture":"UltraSPARC-I","process":"0.5 µm","aliases":["Sun microsystems ultrasparc stp1030bga-143"],"fields":[{"key":"Model name","value":"UltraSPARC-I 143MHz","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Sun Microsystems","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Texas Instruments","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"UltraSPARC-I 143MHz","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"STP103OBGA-143","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 2, 1995","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 2, 1995","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"UltraSPARC","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"UltraSPARC-I","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":143,"unit":"MHz","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"SPARC V9","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"UltraSPARC-I","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.5,"unit":"µm","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":5200000,"unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":310,"unit":"mm²","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7640-r24897","location":"Sun microsystems/ultrasparc/stp1030bga-143 · revision 24897 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0a89fa287f60903d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-143&oldid=24897","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-512","unit":"","sourceId":"chipswiki-31351-r92104","location":"Template:Packages/sun microsystems/bga-521 · revision 92104 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0ad6381e7cc80c7a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpentium%20m&oldid=10167","sourceDate":"2019-04-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3041-r10167"],"url":"https://museum.vlsi.kr/objects/cw-0ad6381e7cc80c7a"},{"id":"cw-0afa41db79f79ffa","name":"WuDaoKou","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Zhaoxin","year":2017,"process":"28 nm","aliases":["Zhaoxin microarchitectures wudaokou"],"fields":[{"key":"Architecture name","value":"WuDaoKou","unit":"","sourceId":"chipswiki-2224-r7542","location":"Zhaoxin/microarchitectures/wudaokou · revision 7542 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-17. 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Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Little Foot","unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":68,"unit":"mm²","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.1,"unit":"V","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8285-r25971","location":"Amd/k6/amd-k6/300adz · revision 25971 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b1085ded0a721e7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300adz&oldid=25971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8285-r25971"],"url":"https://museum.vlsi.kr/objects/cw-0b1085ded0a721e7"},{"id":"cw-0b1439f5013e1f6e","name":"Am186EM–20KI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186EM","year":1995,"architecture":"80186","aliases":["Amd am186ex am186em–20ki\\w"],"fields":[{"key":"Model name","value":"Am186EM–20KI\\W","unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186EM–20KI\\W","unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EM–20KI\\W","unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186EM","unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"5 MT/s","unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14657-r44718","location":"Amd/am186ex/am186em–20ki\\w · revision 44718 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-0b1439f5013e1f6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320ki%5Cw&oldid=44718","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14657-r44718"],"url":"https://museum.vlsi.kr/objects/cw-0b1439f5013e1f6e"},{"id":"cw-0b394cfb4e5fb214","name":"EyeQ1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Mobileye","year":2008,"architecture":"ARM946E","process":"180 nm","aliases":["Mobileye eyeq eyeq1"],"fields":[{"key":"Model name","value":"EyeQ1","unit":"","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Mobileye","unit":"","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"EyeQ1","unit":"","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Automotive","unit":"","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 8, 2004","unit":"","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2008,"unit":"","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EyeQ","unit":"","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":110,"unit":"MHz","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv5","unit":"","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM946E","unit":"","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM946E","unit":"","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.8,"unit":"V","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2.5,"unit":"W","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":120,"unit":"°C","sourceId":"chipswiki-2937-r9832","location":"Mobileye/eyeq/eyeq1 · revision 9832 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-0b394cfb4e5fb214","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq1&oldid=9832","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2937-r9832"],"url":"https://museum.vlsi.kr/objects/cw-0b394cfb4e5fb214"},{"id":"cw-0b41a9abc75abb88","name":"K6","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":1997,"process":"350 nm","aliases":["Amd microarchitectures k6"],"fields":[{"key":"Architecture name","value":"K6","unit":"","sourceId":"chipswiki-2478-r8461","location":"Amd/microarchitectures/k6 · revision 8461 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-0b41a9abc75abb88","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6&oldid=8461","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-2478-r8461","location":"Amd/microarchitectures/k6 · revision 8461 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-0b41a9abc75abb88","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6&oldid=8461","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-2478-r8461","location":"Amd/microarchitectures/k6 · revision 8461 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-0b41a9abc75abb88","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6&oldid=8461","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"April 2, 1997","unit":"","sourceId":"chipswiki-2478-r8461","location":"Amd/microarchitectures/k6 · revision 8461 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-0b41a9abc75abb88","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6&oldid=8461","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-2478-r8461","location":"Amd/microarchitectures/k6 · revision 8461 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-0b41a9abc75abb88","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6&oldid=8461","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-2478-r8461","location":"Amd/microarchitectures/k6 · revision 8461 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-0b41a9abc75abb88","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6&oldid=8461","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-2478-r8461","location":"Amd/microarchitectures/k6 · revision 8461 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-0b41a9abc75abb88","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6&oldid=8461","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"K5","unit":"","sourceId":"chipswiki-2478-r8461","location":"Amd/microarchitectures/k6 · revision 8461 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-0b41a9abc75abb88","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6&oldid=8461","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"K6-2","unit":"","sourceId":"chipswiki-2478-r8461","location":"Amd/microarchitectures/k6 · revision 8461 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-22. Not an independent measurement.","entityId":"cw-0b41a9abc75abb88","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6&oldid=8461","sourceDate":"2019-05-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2478-r8461"],"url":"https://museum.vlsi.kr/objects/cw-0b41a9abc75abb88"},{"id":"cw-0b5a522cab4602f4","name":"i486SX2-50","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486SX2","year":null,"architecture":"80486","process":"800 nm","aliases":["Intel 80486 486sx2-50"],"fields":[{"key":"Model name","value":"Intel i486SX2-50","unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486SX2-50","unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486SX2-50","unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486SX250","unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486SX2","unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":50,"unit":"MHz","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"25 MT/s","unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX845","unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SX2","unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":900000,"unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8077-r25728","location":"Intel/80486/486sx2-50 · revision 25728 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5a522cab4602f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx2-50&oldid=25728","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8077-r25728"],"url":"https://museum.vlsi.kr/objects/cw-0b5a522cab4602f4"},{"id":"cw-0b5c6b0356ce6f4b","name":"CN3005-300 CP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3000","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3005-300bg350-cp"],"fields":[{"key":"Model name","value":"Cavium CN3005-300 CP","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3005-300 CP","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3005-300BG350-CP","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3000","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":300,"unit":"MHz","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-350","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":24,"unit":"KiB","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1,017 MiB/s","unit":"","sourceId":"chipswiki-8281-r25941","location":"Cavium/octeon/cn3005-300bg350-cp · revision 25941 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0b5c6b0356ce6f4b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-cp&oldid=25941","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8281-r25941"],"url":"https://museum.vlsi.kr/objects/cw-0b5c6b0356ce6f4b"},{"id":"cw-0b857f66e4e9827a","name":"Celeron J3060","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"J3000","year":2016,"architecture":"Airmont","process":"14 nm","aliases":["Intel celeron j3060"],"fields":[{"key":"Model name","value":"Intel Celeron J3060","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J3060","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066501715934","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2KR","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 15, 2016","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 15, 2016","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"J3000","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2480,"unit":"MHz","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"IDI","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Braswell","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA1170","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":48,"unit":"KiB","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x24 KiB","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-6864-r21420","location":"Intel/celeron/j3060 · revision 21420 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-0b857f66e4e9827a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3060&oldid=21420","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6864-r21420"],"url":"https://museum.vlsi.kr/objects/cw-0b857f66e4e9827a"},{"id":"cw-0baed40de207f498","name":"Ryzen Embedded V1807B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"V1000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen embedded v1807b"],"fields":[{"key":"Model name","value":"Ryzen Embedded V1807B","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"V1807B","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YE1807C3T4MFB","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Embedded","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"V1000","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3350,"unit":"MHz","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Great Horned Owl","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. 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Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 11","unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":11,"unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-510-r1029","location":"Amd/ryzen embedded/v1807b · revision 1029 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1807b&oldid=1029","sourceDate":"2022-02-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FP5","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1140,"unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.7-1.0 mm","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":35,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.38,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-17. Not an independent measurement.","entityId":"cw-0baed40de207f498","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-510-r1029","chipswiki-31111-r91577"],"url":"https://museum.vlsi.kr/objects/cw-0baed40de207f498"},{"id":"cw-0bb6198302668d55","name":"Core i5-6500TE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i5 i5-6500te"],"fields":[{"key":"Model name","value":"Core i5-6500TE","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-6500TE","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2LR","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-6000","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7916-r25454","location":"Intel/core i5/i5-6500te · revision 25454 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6500te&oldid=25454","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0bb6198302668d55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7916-r25454","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-0bb6198302668d55"},{"id":"cw-0bcd231e2f0bd33e","name":"Gen3","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2004,"aliases":["Intel microarchitectures gen3"],"fields":[{"key":"Architecture name","value":"Gen3","unit":"","sourceId":"chipswiki-15959-r52684","location":"Intel/microarchitectures/gen3 · revision 52684 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. 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Not an independent measurement.","entityId":"cw-0bcd231e2f0bd33e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen3&oldid=52684","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-15959-r52684","location":"Intel/microarchitectures/gen3 · revision 52684 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-0bcd231e2f0bd33e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen3&oldid=52684","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2004,"unit":"","sourceId":"chipswiki-15959-r52684","location":"Intel/microarchitectures/gen3 · revision 52684 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-0bcd231e2f0bd33e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen3&oldid=52684","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Gen2","unit":"","sourceId":"chipswiki-15959-r52684","location":"Intel/microarchitectures/gen3 · revision 52684 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-0bcd231e2f0bd33e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen3&oldid=52684","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gen3.5","unit":"","sourceId":"chipswiki-15959-r52684","location":"Intel/microarchitectures/gen3 · revision 52684 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-0bcd231e2f0bd33e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen3&oldid=52684","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-15959-r52684"],"url":"https://museum.vlsi.kr/objects/cw-0bcd231e2f0bd33e"},{"id":"cw-0bfd02eaee71109a","name":"EPYC 7543P","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 7543p"],"fields":[{"key":"Model name","value":"EPYC 7543P","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. 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Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7543P","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000341","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000341WOF","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. 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Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. 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Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":225,"unit":"W","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32 × 32 KiB","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32 × 32 KiB","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32 × 512 KiB","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8 × 32 MiB","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-751-r1793","location":"Amd/epyc/7543p · revision 1793 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-0bfd02eaee71109a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543p&oldid=1793","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-751-r1793"],"url":"https://museum.vlsi.kr/objects/cw-0bfd02eaee71109a"},{"id":"cw-0c415db6ea9b69d7","name":"Silvermont","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2013,"process":"22 nm","aliases":["Intel microarchitectures silvermont"],"fields":[{"key":"Architecture name","value":"Silvermont","unit":"","sourceId":"chipswiki-1825-r6144","location":"Intel/microarchitectures/silvermont · revision 6144 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-25. 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Not an independent measurement.","entityId":"cw-0c415db6ea9b69d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsilvermont&oldid=6144","sourceDate":"2019-09-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2013,"unit":"","sourceId":"chipswiki-1825-r6144","location":"Intel/microarchitectures/silvermont · revision 6144 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-25. Not an independent measurement.","entityId":"cw-0c415db6ea9b69d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsilvermont&oldid=6144","sourceDate":"2019-09-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-1825-r6144","location":"Intel/microarchitectures/silvermont · revision 6144 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-25. Not an independent measurement.","entityId":"cw-0c415db6ea9b69d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsilvermont&oldid=6144","sourceDate":"2019-09-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-1825-r6144","location":"Intel/microarchitectures/silvermont · revision 6144 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-25. Not an independent measurement.","entityId":"cw-0c415db6ea9b69d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsilvermont&oldid=6144","sourceDate":"2019-09-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-1825-r6144","location":"Intel/microarchitectures/silvermont · revision 6144 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-25. Not an independent measurement.","entityId":"cw-0c415db6ea9b69d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsilvermont&oldid=6144","sourceDate":"2019-09-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1825-r6144","location":"Intel/microarchitectures/silvermont · revision 6144 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-25. Not an independent measurement.","entityId":"cw-0c415db6ea9b69d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsilvermont&oldid=6144","sourceDate":"2019-09-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1825-r6144","location":"Intel/microarchitectures/silvermont · revision 6144 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"2 Cores","note":"Source-reported parameter; source revision 2019-09-25. Not an independent measurement.","entityId":"cw-0c415db6ea9b69d7","scope":"2 Cores","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsilvermont&oldid=6144","sourceDate":"2019-09-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Tangier","unit":"","sourceId":"chipswiki-1825-r6144","location":"Intel/microarchitectures/silvermont · revision 6144 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-25. Not an independent measurement.","entityId":"cw-0c415db6ea9b69d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsilvermont&oldid=6144","sourceDate":"2019-09-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Valleyview","unit":"","sourceId":"chipswiki-1825-r6144","location":"Intel/microarchitectures/silvermont · revision 6144 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2019-09-25. Not an independent measurement.","entityId":"cw-0c415db6ea9b69d7","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsilvermont&oldid=6144","sourceDate":"2019-09-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Avoton","unit":"","sourceId":"chipswiki-1825-r6144","location":"Intel/microarchitectures/silvermont · revision 6144 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2019-09-25. Not an independent measurement.","entityId":"cw-0c415db6ea9b69d7","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsilvermont&oldid=6144","sourceDate":"2019-09-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rangeley","unit":"","sourceId":"chipswiki-1825-r6144","location":"Intel/microarchitectures/silvermont · revision 6144 · {{microarchitecture}} / core name 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 4","note":"Source-reported parameter; source revision 2019-09-25. Not an independent measurement.","entityId":"cw-0c415db6ea9b69d7","scope":"core name 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsilvermont&oldid=6144","sourceDate":"2019-09-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Saltwell","unit":"","sourceId":"chipswiki-1825-r6144","location":"Intel/microarchitectures/silvermont · revision 6144 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-25. Not an independent measurement.","entityId":"cw-0c415db6ea9b69d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsilvermont&oldid=6144","sourceDate":"2019-09-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Airmont","unit":"","sourceId":"chipswiki-1825-r6144","location":"Intel/microarchitectures/silvermont · revision 6144 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-25. Not an independent measurement.","entityId":"cw-0c415db6ea9b69d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsilvermont&oldid=6144","sourceDate":"2019-09-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1825-r6144"],"url":"https://museum.vlsi.kr/objects/cw-0c415db6ea9b69d7"},{"id":"cw-0c4e96a0c783b8a1","name":"Ryzen 5 PRO 1500","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Ryzen PRO","year":2017,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 5 pro 1500"],"fields":[{"key":"Model name","value":"Ryzen 5 PRO 1500","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 1500","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD150BBBM4GAE","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 29, 2017","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 29, 2017","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Ryzen PRO","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Summit Ridge","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x8 MiB","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-7354-r23749","location":"Amd/ryzen 5/pro 1500 · revision 23749 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201500&oldid=23749","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-0c4e96a0c783b8a1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7354-r23749","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-0c4e96a0c783b8a1"},{"id":"cw-0c54f3e33fe6e575","name":"CG80286-10","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"CG80286","year":1984,"architecture":"80286","process":"1.5 µm","aliases":["Amd am286 cg80286-10"],"fields":[{"key":"Model name","value":"CG80286-10","unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CG80286-10","unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CG80286","unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":10,"unit":"MHz","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":134000,"unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":73,"unit":"mm²","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-68","unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CPGA-68","unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8602-r26800","location":"Amd/am286/cg80286-10 · revision 26800 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c54f3e33fe6e575","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fcg80286-10&oldid=26800","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8602-r26800"],"url":"https://museum.vlsi.kr/objects/cw-0c54f3e33fe6e575"},{"id":"cw-0c69039b16581f0f","name":"Xeon E5-2667 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2667 v4"],"fields":[{"key":"Model name","value":"Xeon E5-2667 v4","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2667 v4","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002041900","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2P5","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":135,"unit":"W","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":25,"unit":"MiB","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x2.5 MiB","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-2132-r7099","location":"Intel/xeon e5/e5-2667 v4 · revision 7099 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-01. Not an independent measurement.","entityId":"cw-0c69039b16581f0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2667%20v4&oldid=7099","sourceDate":"2019-08-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2132-r7099"],"url":"https://museum.vlsi.kr/objects/cw-0c69039b16581f0f"},{"id":"cw-0c961390e626d792","name":"Core i7-4770HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":2014,"architecture":"Haswell","process":"22 nm","aliases":["Intel core i7 i7-4770hq"],"fields":[{"key":"Model name","value":"Intel Core i7-4770HQ","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-4770HQ","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8064701956100","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 20, 2014","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 20, 2014","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR1ZW","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Haswell","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Shark Bay","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7870-r25373","location":"Intel/core i7/i7-4770hq · revision 25373 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0c961390e626d792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7870-r25373","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-0c961390e626d792"},{"id":"cw-0c961b2886be639a","name":"K6-III","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":1999,"process":"250 nm","aliases":["Amd microarchitectures k6-iii"],"fields":[{"key":"Architecture name","value":"K6-III","unit":"","sourceId":"chipswiki-8755-r27206","location":"Amd/microarchitectures/k6-iii · revision 27206 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-0c961b2886be639a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-iii&oldid=27206","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8755-r27206","location":"Amd/microarchitectures/k6-iii · revision 27206 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-0c961b2886be639a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-iii&oldid=27206","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8755-r27206","location":"Amd/microarchitectures/k6-iii · revision 27206 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-0c961b2886be639a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-iii&oldid=27206","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"February 22, 1999","unit":"","sourceId":"chipswiki-8755-r27206","location":"Amd/microarchitectures/k6-iii · revision 27206 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-0c961b2886be639a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-iii&oldid=27206","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-8755-r27206","location":"Amd/microarchitectures/k6-iii · revision 27206 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-0c961b2886be639a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-iii&oldid=27206","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8755-r27206","location":"Amd/microarchitectures/k6-iii · revision 27206 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-0c961b2886be639a","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-iii&oldid=27206","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8755-r27206","location":"Amd/microarchitectures/k6-iii · revision 27206 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-0c961b2886be639a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-iii&oldid=27206","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"K6-2","unit":"","sourceId":"chipswiki-8755-r27206","location":"Amd/microarchitectures/k6-iii · revision 27206 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-0c961b2886be639a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-iii&oldid=27206","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"K7","unit":"","sourceId":"chipswiki-8755-r27206","location":"Amd/microarchitectures/k6-iii · revision 27206 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-0c961b2886be639a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-iii&oldid=27206","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8755-r27206"],"url":"https://museum.vlsi.kr/objects/cw-0c961b2886be639a"},{"id":"cw-0cd258644259e87b","name":"Core i3-8100H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-8100h"],"fields":[{"key":"Model name","value":"Core i3-8100H","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8100H","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 3, 2018","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 5, 2018","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-8000","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake H","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":23,"unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-5262-r17210","location":"Intel/core i3/i3-8100h · revision 17210 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8100h&oldid=17210","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-0cd258644259e87b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5262-r17210","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-0cd258644259e87b"},{"id":"cw-0ce448c63c403478","name":"Am486DX4-120V8T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX4V","year":1995,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx4-120v8t"],"fields":[{"key":"Model name","value":"Am486DX4-120V8T","unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX4-120V8T","unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX4-120V8T","unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX4V","unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":120,"unit":"MHz","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"40 MT/s","unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX4V","unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8550-r26746","location":"Amd/am486/am486dx4-120v8t · revision 26746 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ce448c63c403478","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120v8t&oldid=26746","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8550-r26746"],"url":"https://museum.vlsi.kr/objects/cw-0ce448c63c403478"},{"id":"cw-0d0750cb2da8286a","name":"CN3120-400 CP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3120-400bg868-cp"],"fields":[{"key":"Model name","value":"Cavium CN3120-400 CP","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3120-400 CP","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3120-400BG868-CP","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":80,"unit":"KiB","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x8 KiB","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-cp&oldid=25909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8249-r25909","location":"Cavium/octeon/cn3120-400bg868-cp · revision 25909 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d0750cb2da8286a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8249-r25909","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-0d0750cb2da8286a"},{"id":"cw-0d18648949b06924","name":"Centriq 2434","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"2400","year":2017,"architecture":"Falkor","process":"10 nm","aliases":["Qualcomm centriq 2434"],"fields":[{"key":"Model name","value":"Centriq 2434","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":2434,"unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 8, 2017","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 8, 2017","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Centriq","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2400,"unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Falkor","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":18000000000,"unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":398,"unit":"mm²","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":40,"unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":110,"unit":"W","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":3.75,"unit":"MiB","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2.5,"unit":"MiB","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"40x64 KiB","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"40x32 KiB","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":10,"unit":"MiB","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x512 KiB","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":50,"unit":"MiB","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x5 MiB","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":6,"unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-7672-r24939","location":"Qualcomm/centriq/2434 · revision 24939 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fcentriq%2F2434&oldid=24939","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2808","unit":"","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":2808,"unit":"","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":55,"unit":"mm","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":55,"unit":"mm","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2808","unit":"","sourceId":"chipswiki-31367-r92153","location":"Template:Packages/qualcomm/fclga-2808 · revision 92153 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d18648949b06924","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fqualcomm%2Ffclga-2808&oldid=92153","sourceDate":"2017-11-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7672-r24939","chipswiki-31367-r92153"],"url":"https://museum.vlsi.kr/objects/cw-0d18648949b06924"},{"id":"cw-0d6d26a0a26d1e1c","name":"N80C286-10","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N80C286","year":1990,"architecture":"80286","process":"800 nm","aliases":["Amd am286 n80c286-10"],"fields":[{"key":"Model name","value":"N80C286-10","unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N80C286-10","unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1990,"unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N80C286","unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":10,"unit":"MHz","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":165,"unit":"°C","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-68","unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PLCC-68","unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8595-r26793","location":"Amd/am286/n80c286-10 · revision 26793 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d6d26a0a26d1e1c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80c286-10&oldid=26793","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8595-r26793"],"url":"https://museum.vlsi.kr/objects/cw-0d6d26a0a26d1e1c"},{"id":"cw-0d903aaf016363b1","name":"Ryzen 3 PRO 3200GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 3 pro 3200ge"],"fields":[{"key":"Model name","value":"Ryzen 3 PRO 3200GE","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 3200GE","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD320BC6M4MFH","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-1553-r5094","location":"Amd/ryzen 3/pro 3200ge · revision 5094 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-0d903aaf016363b1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%203200ge&oldid=5094","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1553-r5094"],"url":"https://museum.vlsi.kr/objects/cw-0d903aaf016363b1"},{"id":"cw-0d9a9a9f35abd01e","name":"AMD-K6-166ALYD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Desktop K6","year":1997,"architecture":"K6","process":"350 nm","aliases":["Amd k6 amd-k6-166alyd"],"fields":[{"key":"Model name","value":"AMD-K6-166ALYD","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-166ALYD","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-166ALYD","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1997","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 1997","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Desktop K6","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":166.66,"unit":"MHz","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"6k86","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":162,"unit":"mm²","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.9,"unit":"V","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8298-r25987","location":"Amd/k6/amd-k6-166alyd · revision 25987 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0d9a9a9f35abd01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-166alyd&oldid=25987","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8298-r25987"],"url":"https://museum.vlsi.kr/objects/cw-0d9a9a9f35abd01e"},{"id":"cw-0dcdad200f4d86a2","name":"Core i3-6300","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i3 i3-6300"],"fields":[{"key":"Model name","value":"Core i3-6300","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-6300","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201926905","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80662I36300","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80662I36300","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2HA","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-6000","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3800,"unit":"MHz","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7979-r25556","location":"Intel/core i3/i3-6300 · revision 25556 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6300&oldid=25556","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0dcdad200f4d86a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7979-r25556","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-0dcdad200f4d86a2"},{"id":"cw-0dff6c1950980f6f","name":"Ryzen Threadripper PRO 5945WX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5900","year":2022,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen threadripper pro 5945wx"],"fields":[{"key":"Model name","value":"Ryzen Threadripper PRO 5945WX","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. 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Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 5945WX","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000448","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 8, 2022","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Threadripper","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5900,"unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":4100,"unit":"MHz","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4500,"unit":"MHz","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"WRX80","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. 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Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12 × 32 KiB","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12 × 32 KiB","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12 × 512 KiB","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2 × 32 MiB","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"204.8 GB/s","unit":"","sourceId":"chipswiki-395-r841","location":"Amd/ryzen threadripper/pro 5945wx · revision 841 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205945wx&oldid=841","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OLGA","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.87,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":75.4,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":58.5,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":6.26,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-0dff6c1950980f6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-395-r841","chipswiki-31095-r91554"],"url":"https://museum.vlsi.kr/objects/cw-0dff6c1950980f6f"},{"id":"cw-0e3b7c9e6e73f0b0","name":"Core i7-980X Extreme Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Core i7-900","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i7ee i7-980x"],"fields":[{"key":"Model name","value":"Core i7-980X Extreme Edition","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-980X","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80613003543AE","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80613I7980X","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2010","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 16, 2010","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Core i7-900","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3333,"unit":"MHz","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBUZ","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Boxboro","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Gulftown","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A0","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":239,"unit":"mm²","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":24,"unit":"GiB","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA1366","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7819-r25274","location":"Intel/core i7ee/i7-980x · revision 25274 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e3b7c9e6e73f0b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-980x&oldid=25274","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7819-r25274"],"url":"https://museum.vlsi.kr/objects/cw-0e3b7c9e6e73f0b0"},{"id":"cw-0e5177c1cb26a8b6","name":"K6-2/500AHX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-500ahx"],"fields":[{"key":"Model name","value":"K6-2/500AHX","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/500AHX","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/500AHX","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 26, 1999","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 11, 1999","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":499.99,"unit":"MHz","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.4,"unit":"V","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8335-r26030","location":"Amd/k6-2/k6-2-500ahx · revision 26030 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e5177c1cb26a8b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500ahx&oldid=26030","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8335-r26030"],"url":"https://museum.vlsi.kr/objects/cw-0e5177c1cb26a8b6"},{"id":"cw-0e590e019fa07c3a","name":"Atom Z515","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z500","year":2009,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z515"],"fields":[{"key":"Model name","value":"Atom Z515","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z515","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AC80566UC009DV","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLGMG","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 8, 2009","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 8, 2009","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z500","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"400 MT/s","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Menlow","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Poulsbo","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Silverthorne","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":28,"unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47212207,"unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":24.18,"unit":"mm²","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"650 mW","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8067-r25703","location":"Intel/atom/z515 · revision 25703 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz515&oldid=25703","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-441","unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":441,"unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13,"unit":"mm","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":14,"unit":"mm","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e590e019fa07c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8067-r25703","chipswiki-31513-r92656"],"url":"https://museum.vlsi.kr/objects/cw-0e590e019fa07c3a"},{"id":"cw-0e6219c79209001e","name":"Helio P30","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio P","year":2017,"architecture":"Cortex-A53","process":"16 nm","aliases":["Mediatek helio p30"],"fields":[{"key":"Model name","value":"Helio P30","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P30","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 28, 2017","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"Aug 28, 2017","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio P","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1650,"unit":"MHz","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2300,"unit":"MHz","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":6,"unit":"GiB","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3200","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G71","unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":950,"unit":"MHz","sourceId":"chipswiki-2203-r7454","location":"Mediatek/helio/p30 · revision 7454 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-26. Not an independent measurement.","entityId":"cw-0e6219c79209001e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp30&oldid=7454","sourceDate":"2019-06-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2203-r7454"],"url":"https://museum.vlsi.kr/objects/cw-0e6219c79209001e"},{"id":"cw-0e6fbef781db7e68","name":"K6-2/400AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-400afr"],"fields":[{"key":"Model name","value":"K6-2/400AFR","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/400AFR","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/400AFR","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 15, 1999","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.99,"unit":"MHz","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8352-r26047","location":"Amd/k6-2/k6-2-400afr · revision 26047 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0e6fbef781db7e68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afr&oldid=26047","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8352-r26047"],"url":"https://museum.vlsi.kr/objects/cw-0e6fbef781db7e68"},{"id":"cw-0ea6503d1c952c65","name":"CN3010-500 CP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3000","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3010-500bg525-cp"],"fields":[{"key":"Model name","value":"Cavium CN3010-500 CP","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3010-500 CP","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3010-500BG525-CP","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3000","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-525","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":24,"unit":"KiB","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0ea6503d1c952c65","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-cp&oldid=25931","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":1.986,"unit":"GiB/s","sourceId":"chipswiki-8271-r25931","location":"Cavium/octeon/cn3010-500bg525-cp · revision 25931 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0f004c20751faa10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1cc&oldid=26683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3.125,"unit":"MHz","sourceId":"chipswiki-8490-r26683","location":"Amd/am9080/am9080a-1cc · revision 26683 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-0f004c20751faa10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1cc&oldid=26683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8490-r26683","location":"Amd/am9080/am9080a-1cc · revision 26683 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f004c20751faa10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1cc&oldid=26683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8490-r26683","location":"Amd/am9080/am9080a-1cc · revision 26683 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f004c20751faa10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1cc&oldid=26683","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8490-r26683"],"url":"https://museum.vlsi.kr/objects/cw-0f004c20751faa10"},{"id":"cw-0f4b8839bf1ae6b4","name":"Xeon E5-2670 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2670 v4"],"fields":[{"key":"Model name","value":"Xeon E5-2670 v4","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2670 v4","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4700000000,"unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":306.18,"unit":"mm²","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":14,"unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":28,"unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":120,"unit":"W","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":448,"unit":"KiB","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":448,"unit":"KiB","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3.5,"unit":"MiB","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x256 KiB","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35,"unit":"MiB","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x2.5 MiB","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7731-r25107","location":"Intel/xeon e5/e5-2670 v4 · revision 25107 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f4b8839bf1ae6b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2670%20v4&oldid=25107","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7731-r25107"],"url":"https://museum.vlsi.kr/objects/cw-0f4b8839bf1ae6b4"},{"id":"cw-0f7f761413fb418b","name":"Duron 650 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2000,"architecture":"K7","process":"180 nm","aliases":["Amd duron d650ast1b"],"fields":[{"key":"Model name","value":"Duron 650","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 650","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D650AST1B","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2000","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 19, 2000","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":650,"unit":"MHz","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":24.3,"unit":"W","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8440-r26148","location":"Amd/duron/d650ast1b · revision 26148 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-0f7f761413fb418b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650ast1b&oldid=26148","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8440-r26148"],"url":"https://museum.vlsi.kr/objects/cw-0f7f761413fb418b"},{"id":"cw-0f9a89adf883c7b3","name":"ISAAC","kind":"sku","entityType":"product-model","subtype":"sku","company":"Movidius","year":null,"process":"65 nm","aliases":["Movidius isaac"],"fields":[{"key":"Model name","value":"ISAAC","unit":"","sourceId":"chipswiki-6976-r21797","location":"Movidius/isaac · revision 21797 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-0f9a89adf883c7b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fisaac&oldid=21797","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Movidius","unit":"","sourceId":"chipswiki-6976-r21797","location":"Movidius/isaac · revision 21797 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-0f9a89adf883c7b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fisaac&oldid=21797","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-6976-r21797","location":"Movidius/isaac · revision 21797 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-0f9a89adf883c7b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fisaac&oldid=21797","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Movidius","unit":"","sourceId":"chipswiki-6976-r21797","location":"Movidius/isaac · revision 21797 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-0f9a89adf883c7b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fisaac&oldid=21797","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6976-r21797","location":"Movidius/isaac · revision 21797 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-0f9a89adf883c7b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fisaac&oldid=21797","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2007,"unit":"","sourceId":"chipswiki-6976-r21797","location":"Movidius/isaac · revision 21797 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-0f9a89adf883c7b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fisaac&oldid=21797","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-6976-r21797","location":"Movidius/isaac · revision 21797 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-0f9a89adf883c7b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fisaac&oldid=21797","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6976-r21797","location":"Movidius/isaac · revision 21797 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-0f9a89adf883c7b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fisaac&oldid=21797","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6976-r21797"],"url":"https://museum.vlsi.kr/objects/cw-0f9a89adf883c7b3"},{"id":"cw-0fc1b4dd3a118834","name":"Xeon Gold 6230N","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6230n"],"fields":[{"key":"Model name","value":"Xeon Gold 6230N","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6230N","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":640,"unit":"KiB","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":20,"unit":"MiB","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x1 MiB","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":27.5,"unit":"MiB","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"20x1.375 MiB","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1490-r4941","location":"Intel/xeon gold/6230n · revision 4941 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-0fc1b4dd3a118834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230n&oldid=4941","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1490-r4941"],"url":"https://museum.vlsi.kr/objects/cw-0fc1b4dd3a118834"},{"id":"cw-1016a0d2370255b7","name":"Ryzen 3 2300U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000U","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 3 2300u"],"fields":[{"key":"Model name","value":"Ryzen 3 2300U","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2300U","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 8, 2018","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 8, 2018","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"2000U","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-6284-r19496","location":"Amd/ryzen 3/2300u · revision 19496 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300u&oldid=19496","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FP5","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1140,"unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.7-1.0 mm","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":35,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.38,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-1016a0d2370255b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6284-r19496","chipswiki-31111-r91577"],"url":"https://museum.vlsi.kr/objects/cw-1016a0d2370255b7"},{"id":"cw-1053e2592b9ed4fb","name":"CN3120-400 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3120-400bg868-exp"],"fields":[{"key":"Model name","value":"Cavium CN3120-400 EXP","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3120-400 EXP","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3120-400BG868-EXP","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":80,"unit":"KiB","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x8 KiB","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8248-r25908","location":"Cavium/octeon/cn3120-400bg868-exp · revision 25908 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-exp&oldid=25908","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1053e2592b9ed4fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8248-r25908","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-1053e2592b9ed4fb"},{"id":"cw-10944a2c62fd7c58","name":"AMD-K6-233ANR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Desktop K6","year":1997,"architecture":"K6","process":"350 nm","aliases":["Amd k6 amd-k6-233anr"],"fields":[{"key":"Model name","value":"AMD-K6-233ANR","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-233ANR","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-233ANR","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1997","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 1997","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Desktop K6","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":233.33,"unit":"MHz","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"6k86","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":162,"unit":"mm²","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.9,"unit":"V","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8294-r25982","location":"Amd/k6/amd-k6-233anr · revision 25982 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-10944a2c62fd7c58","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233anr&oldid=25982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8294-r25982"],"url":"https://museum.vlsi.kr/objects/cw-10944a2c62fd7c58"},{"id":"cw-10afdc74ea84410c","name":"Ryzen 3 PRO 1200","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Ryzen PRO","year":null,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 3 pro 1200"],"fields":[{"key":"Model name","value":"Ryzen 3 PRO 1200","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 1200","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD120BBBM4KAE","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 29, 2017","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Ryzen PRO","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Summit Ridge","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x8 MiB","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%201200&oldid=23751","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-7356-r23751","location":"Amd/ryzen 3/pro 1200 · revision 23751 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. 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Not an independent measurement.","entityId":"cw-10afdc74ea84410c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. 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Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-2125","unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. 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Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3LM","unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. 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Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 29, 2017","unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-2000","unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. 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Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x1 MiB","unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8.25,"unit":"MiB","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.375 MiB","unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-2532-r8694","location":"Intel/xeon w/w-2125 · revision 8694 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-10e7209180ab47a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2125&oldid=8694","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2532-r8694"],"url":"https://museum.vlsi.kr/objects/cw-10e7209180ab47a5"},{"id":"cw-1107fbb4d4ee03c2","name":"CN3850-400 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3850-400bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN3850-400 SCP","unit":"","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x8 KiB","unit":"","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8209-r25868","location":"Cavium/octeon/cn3850-400bg1521-scp · revision 25868 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-scp&oldid=25868","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1107fbb4d4ee03c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8209-r25868","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-1107fbb4d4ee03c2"},{"id":"cw-1128ec41a86657e0","name":"EyeQ4","kind":"sku","entityType":"product-model","subtype":"sku","company":"Mobileye","year":2018,"process":"28 nm","aliases":["Mobileye eyeq eyeq4"],"fields":[{"key":"Model name","value":"EyeQ4","unit":"","sourceId":"chipswiki-2466-r8374","location":"Mobileye/eyeq/eyeq4 · revision 8374 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-26. Not an independent measurement.","entityId":"cw-1128ec41a86657e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq4&oldid=8374","sourceDate":"2019-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Mobileye","unit":"","sourceId":"chipswiki-2466-r8374","location":"Mobileye/eyeq/eyeq4 · revision 8374 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-26. Not an independent measurement.","entityId":"cw-1128ec41a86657e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq4&oldid=8374","sourceDate":"2019-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"STMicroelectronics","unit":"","sourceId":"chipswiki-2466-r8374","location":"Mobileye/eyeq/eyeq4 · revision 8374 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-26. Not an independent measurement.","entityId":"cw-1128ec41a86657e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq4&oldid=8374","sourceDate":"2019-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Automotive","unit":"","sourceId":"chipswiki-2466-r8374","location":"Mobileye/eyeq/eyeq4 · revision 8374 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-26. Not an independent measurement.","entityId":"cw-1128ec41a86657e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq4&oldid=8374","sourceDate":"2019-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 4, 2015","unit":"","sourceId":"chipswiki-2466-r8374","location":"Mobileye/eyeq/eyeq4 · revision 8374 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-26. Not an independent measurement.","entityId":"cw-1128ec41a86657e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq4&oldid=8374","sourceDate":"2019-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2018","unit":"","sourceId":"chipswiki-2466-r8374","location":"Mobileye/eyeq/eyeq4 · revision 8374 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-26. Not an independent measurement.","entityId":"cw-1128ec41a86657e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq4&oldid=8374","sourceDate":"2019-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EyeQ","unit":"","sourceId":"chipswiki-2466-r8374","location":"Mobileye/eyeq/eyeq4 · revision 8374 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-26. Not an independent measurement.","entityId":"cw-1128ec41a86657e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq4&oldid=8374","sourceDate":"2019-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-2466-r8374","location":"Mobileye/eyeq/eyeq4 · revision 8374 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-26. Not an independent measurement.","entityId":"cw-1128ec41a86657e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq4&oldid=8374","sourceDate":"2019-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2466-r8374","location":"Mobileye/eyeq/eyeq4 · revision 8374 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-26. Not an independent measurement.","entityId":"cw-1128ec41a86657e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq4&oldid=8374","sourceDate":"2019-05-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-2466-r8374","location":"Mobileye/eyeq/eyeq4 · revision 8374 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-26. Not an independent measurement.","entityId":"cw-1128ec41a86657e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq4&oldid=8374","sourceDate":"2019-05-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2466-r8374"],"url":"https://museum.vlsi.kr/objects/cw-1128ec41a86657e0"},{"id":"cw-11485a61b600a69b","name":"Xeon Platinum 8176M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8176m"],"fields":[{"key":"Model name","value":"Xeon Platinum 8176M","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8176M","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303133605","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR37U","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1468-r4915","location":"Intel/xeon platinum/8176m · revision 4915 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-11485a61b600a69b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176m&oldid=4915","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1468-r4915"],"url":"https://museum.vlsi.kr/objects/cw-11485a61b600a69b"},{"id":"cw-114fcb4d8db6030e","name":"VL86C010","kind":"sku","entityType":"product-model","subtype":"soc","company":"Acorn","year":1987,"architecture":"ARM2","process":"2 µm","aliases":["Vti vl86cx vl86c010"],"fields":[{"key":"Model name","value":"VL86C010","unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Acorn Computers","unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Sanyo","unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"VL86C010","unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VL86C010-10QC","unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C010-10QC","unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VL86C010-12QC","unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C010-12QC","unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1987,"unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"VL86Cx","unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":10,"unit":"MHz","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":12,"unit":"MHz","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv2","unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM2","unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MEMC","unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":2,"unit":"µm","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":27000,"unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":34.13,"unit":"mm²","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"MiB","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"","sourceId":"chipswiki-7633-r24889","location":"Vti/vl86cx/vl86c010 · revision 24889 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvl86c010&oldid=24889","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-84","unit":"","sourceId":"chipswiki-31441-r92366","location":"Template:Packages/vti/plcc-84 · revision 92366 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-84&oldid=92366","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-31441-r92366","location":"Template:Packages/vti/plcc-84 · revision 92366 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-84&oldid=92366","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31441-r92366","location":"Template:Packages/vti/plcc-84 · revision 92366 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-84&oldid=92366","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":29.41,"unit":"mm","sourceId":"chipswiki-31441-r92366","location":"Template:Packages/vti/plcc-84 · revision 92366 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-84&oldid=92366","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":30.35,"unit":"mm","sourceId":"chipswiki-31441-r92366","location":"Template:Packages/vti/plcc-84 · revision 92366 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-84&oldid=92366","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":5.08,"unit":"mm","sourceId":"chipswiki-31441-r92366","location":"Template:Packages/vti/plcc-84 · revision 92366 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-114fcb4d8db6030e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-84&oldid=92366","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7633-r24889","chipswiki-31441-r92366"],"url":"https://museum.vlsi.kr/objects/cw-114fcb4d8db6030e"},{"id":"cw-116553085495d366","name":"Knights Hill","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":null,"process":"10 nm","aliases":["Intel microarchitectures knights hill"],"fields":[{"key":"Architecture name","value":"Knights Hill","unit":"","sourceId":"chipswiki-6405-r20000","location":"Intel/microarchitectures/knights hill · revision 20000 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-116553085495d366","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20hill&oldid=20000","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6405-r20000","location":"Intel/microarchitectures/knights hill · revision 20000 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-116553085495d366","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20hill&oldid=20000","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6405-r20000","location":"Intel/microarchitectures/knights hill · revision 20000 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-116553085495d366","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20hill&oldid=20000","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-6405-r20000","location":"Intel/microarchitectures/knights hill · revision 20000 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-116553085495d366","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20hill&oldid=20000","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-6405-r20000","location":"Intel/microarchitectures/knights hill · revision 20000 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-116553085495d366","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20hill&oldid=20000","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-16","unit":"","sourceId":"chipswiki-6405-r20000","location":"Intel/microarchitectures/knights hill · revision 20000 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-116553085495d366","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20hill&oldid=20000","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Knights Landing","unit":"","sourceId":"chipswiki-6405-r20000","location":"Intel/microarchitectures/knights hill · revision 20000 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-116553085495d366","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20hill&oldid=20000","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Knights Peak","unit":"","sourceId":"chipswiki-6405-r20000","location":"Intel/microarchitectures/knights hill · revision 20000 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-116553085495d366","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20hill&oldid=20000","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6405-r20000"],"url":"https://museum.vlsi.kr/objects/cw-116553085495d366"},{"id":"cw-1169e03a5e79da08","name":"Ryzen 7 2700","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000","year":2018,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 7 2700"],"fields":[{"key":"Model name","value":"Ryzen 7 2700","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":2700,"unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD2700BBM88AF","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 13, 2018","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 19, 2018","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2000,"unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Pinnacle Ridge","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x64 KiB","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x8 MiB","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-2170-r7275","location":"Amd/ryzen 7/2700 · revision 7275 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700&oldid=7275","sourceDate":"2019-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-18. Not an independent measurement.","entityId":"cw-1169e03a5e79da08","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2170-r7275","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-1169e03a5e79da08"},{"id":"cw-1195bffee711f5bc","name":"M1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Apple","year":2020,"architecture":"Firestorm","process":"5 nm (N5)","aliases":["Apple mx m1"],"fields":[{"key":"Model name","value":"M1","unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Apple","unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"M1","unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"APL1102","unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop + Mobile","unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 10, 2020","unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 17, 2020","unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Mx","unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.4","unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Firestorm","unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Firestorm","unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Icestorm","unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"5 nm (N5)","unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":16000000000,"unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":119,"unit":"mm²","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GB","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-490-r976","location":"Apple/mx/m1 · revision 976 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-12. Not an independent measurement.","entityId":"cw-1195bffee711f5bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fmx%2Fm1&oldid=976","sourceDate":"2022-03-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-490-r976"],"url":"https://museum.vlsi.kr/objects/cw-1195bffee711f5bc"},{"id":"cw-1198dbb8732d6f3c","name":"TaiShan v110","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"HiSilicon","year":2019,"process":"7 nm","aliases":["Hisilicon microarchitectures taishan v110"],"fields":[{"key":"Architecture name","value":"TaiShan v110","unit":"","sourceId":"chipswiki-205-r419","location":"Hisilicon/microarchitectures/taishan v110 · revision 419 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-09. Not an independent measurement.","entityId":"cw-1198dbb8732d6f3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fmicroarchitectures%2Ftaishan%20v110&oldid=419","sourceDate":"2022-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"HiSilicon","unit":"","sourceId":"chipswiki-205-r419","location":"Hisilicon/microarchitectures/taishan v110 · revision 419 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-09. Not an independent measurement.","entityId":"cw-1198dbb8732d6f3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fmicroarchitectures%2Ftaishan%20v110&oldid=419","sourceDate":"2022-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-205-r419","location":"Hisilicon/microarchitectures/taishan v110 · revision 419 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-09. Not an independent measurement.","entityId":"cw-1198dbb8732d6f3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fmicroarchitectures%2Ftaishan%20v110&oldid=419","sourceDate":"2022-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2019,"unit":"","sourceId":"chipswiki-205-r419","location":"Hisilicon/microarchitectures/taishan v110 · revision 419 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-09. Not an independent measurement.","entityId":"cw-1198dbb8732d6f3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fmicroarchitectures%2Ftaishan%20v110&oldid=419","sourceDate":"2022-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-205-r419","location":"Hisilicon/microarchitectures/taishan v110 · revision 419 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-09. Not an independent measurement.","entityId":"cw-1198dbb8732d6f3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fmicroarchitectures%2Ftaishan%20v110&oldid=419","sourceDate":"2022-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":32,"unit":"","sourceId":"chipswiki-205-r419","location":"Hisilicon/microarchitectures/taishan v110 · revision 419 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-09. Not an independent measurement.","entityId":"cw-1198dbb8732d6f3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fmicroarchitectures%2Ftaishan%20v110&oldid=419","sourceDate":"2022-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-205-r419","location":"Hisilicon/microarchitectures/taishan v110 · revision 419 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-09. Not an independent measurement.","entityId":"cw-1198dbb8732d6f3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fmicroarchitectures%2Ftaishan%20v110&oldid=419","sourceDate":"2022-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-205-r419","location":"Hisilicon/microarchitectures/taishan v110 · revision 419 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-09-09. Not an independent measurement.","entityId":"cw-1198dbb8732d6f3c","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fmicroarchitectures%2Ftaishan%20v110&oldid=419","sourceDate":"2022-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-205-r419","location":"Hisilicon/microarchitectures/taishan v110 · revision 419 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-09. Not an independent measurement.","entityId":"cw-1198dbb8732d6f3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fmicroarchitectures%2Ftaishan%20v110&oldid=419","sourceDate":"2022-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2-A","unit":"","sourceId":"chipswiki-205-r419","location":"Hisilicon/microarchitectures/taishan v110 · revision 419 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-09. Not an independent measurement.","entityId":"cw-1198dbb8732d6f3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fmicroarchitectures%2Ftaishan%20v110&oldid=419","sourceDate":"2022-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-205-r419","location":"Hisilicon/microarchitectures/taishan v110 · revision 419 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-09-09. Not an independent measurement.","entityId":"cw-1198dbb8732d6f3c","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fmicroarchitectures%2Ftaishan%20v110&oldid=419","sourceDate":"2022-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":1,"unit":"MiB","sourceId":"chipswiki-205-r419","location":"Hisilicon/microarchitectures/taishan v110 · revision 419 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-09-09. Not an independent measurement.","entityId":"cw-1198dbb8732d6f3c","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fmicroarchitectures%2Ftaishan%20v110&oldid=419","sourceDate":"2022-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"TaiShan v100","unit":"","sourceId":"chipswiki-205-r419","location":"Hisilicon/microarchitectures/taishan v110 · revision 419 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-09. Not an independent measurement.","entityId":"cw-1198dbb8732d6f3c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fmicroarchitectures%2Ftaishan%20v110&oldid=419","sourceDate":"2022-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-205-r419"],"url":"https://museum.vlsi.kr/objects/cw-1198dbb8732d6f3c"},{"id":"cw-11af93e02fd9b095","name":"CN3840-500 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3840-500bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN3840-500 EXP","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3840-500 EXP","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3840-500BG1521-EXP","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x8 KiB","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8217-r25876","location":"Cavium/octeon/cn3840-500bg1521-exp · revision 25876 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-exp&oldid=25876","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11af93e02fd9b095","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8217-r25876","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-11af93e02fd9b095"},{"id":"cw-11c7cd2de52afa98","name":"Xeon Platinum 8276","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 8276"],"fields":[{"key":"Model name","value":"Xeon Platinum 8276","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8276,"unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504195501","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF99","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8200,"unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-2563-r8903","location":"Intel/xeon platinum/8276 · revision 8903 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-11c7cd2de52afa98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276&oldid=8903","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2563-r8903"],"url":"https://museum.vlsi.kr/objects/cw-11c7cd2de52afa98"},{"id":"cw-11f530d662ed3268","name":"Ryzen Threadripper PRO 3975WX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3900","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen threadripper pro 3975wx"],"fields":[{"key":"Model name","value":"Ryzen Threadripper PRO 3975WX","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 3975WX","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000086","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000086WOF","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 14, 2020","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Threadripper","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3900,"unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"WRX80","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Castle Peak","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":23540000000,"unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":280,"unit":"W","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32 × 32 KiB","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32 × 32 KiB","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32 × 512 KiB","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8 × 16 MiB","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"204.8 GB/s","unit":"","sourceId":"chipswiki-385-r830","location":"Amd/ryzen threadripper/pro 3975wx · revision 830 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203975wx&oldid=830","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OLGA","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.87,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":75.4,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":58.5,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":6.26,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-11f530d662ed3268","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-385-r830","chipswiki-31095-r91554"],"url":"https://museum.vlsi.kr/objects/cw-11f530d662ed3268"},{"id":"cw-11f6f2071df2a1c0","name":"AM9080A-2PC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080a-2pc"],"fields":[{"key":"Model name","value":"AMD AM9080A-2PC","unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080A-2PC","unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080A-2PC","unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.632,"unit":"MHz","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"DIP-40","unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"DIP","unit":"","sourceId":"chipswiki-8476-r26669","location":"Amd/am9080/am9080a-2pc · revision 26669 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-11f6f2071df2a1c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pc&oldid=26669","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8476-r26669"],"url":"https://museum.vlsi.kr/objects/cw-11f6f2071df2a1c0"},{"id":"cw-12069594e99ece98","name":"Xeon E5-2686 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2686 v4"],"fields":[{"key":"Model name","value":"Xeon E5-2686 v4","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2686 v4","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002685800","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2K8","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7200000000,"unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":456.12,"unit":"mm²","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":145,"unit":"W","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4.5,"unit":"MiB","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x256 KiB","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":45,"unit":"MiB","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x2.5 MiB","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7726-r25101","location":"Intel/xeon e5/e5-2686 v4 · revision 25101 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-12069594e99ece98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7726-r25101"],"url":"https://museum.vlsi.kr/objects/cw-12069594e99ece98"},{"id":"cw-120c796aac0f62d4","name":"Ryzen 3 2200U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000U","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 3 2200u"],"fields":[{"key":"Model name","value":"Ryzen 3 2200U","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2200U","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 8, 2018","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 8, 2018","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"2000U","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x64 KiB","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. 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Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 3","unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-906-r2407","location":"Amd/ryzen 3/2200u · revision 2407 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200u&oldid=2407","sourceDate":"2020-11-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FP5","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. 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Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1140,"unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. 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Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.38,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-20. Not an independent measurement.","entityId":"cw-120c796aac0f62d4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-906-r2407","chipswiki-31111-r91577"],"url":"https://museum.vlsi.kr/objects/cw-120c796aac0f62d4"},{"id":"cw-120d4238994d8152","name":"Xeon D-1557","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1557"],"fields":[{"key":"Model name","value":"Xeon D-1557","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1557","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067402570702","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2M4","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2016","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 24, 2016","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2100,"unit":"MHz","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Y0","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4700000000,"unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":306.18,"unit":"mm²","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x256 KiB","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":18,"unit":"MiB","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.5 MiB","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3735-r11444","location":"Intel/xeon d/d-1557 · revision 11444 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-120d4238994d8152","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1557&oldid=11444","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3735-r11444"],"url":"https://museum.vlsi.kr/objects/cw-120d4238994d8152"},{"id":"cw-1216e0534b993661","name":"Athlon PRO 300U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"300","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd athlon pro 300u"],"fields":[{"key":"Model name","value":"Athlon PRO 300U","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. 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Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 300U","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YM300BC4T2OFG","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 8, 2019","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 8, 2019","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":300,"unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x64 KiB","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 3","unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-2187-r7385","location":"Amd/athlon/pro 300u · revision 7385 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-02. Not an independent measurement.","entityId":"cw-1216e0534b993661","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300u&oldid=7385","sourceDate":"2019-07-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2187-r7385"],"url":"https://museum.vlsi.kr/objects/cw-1216e0534b993661"},{"id":"cw-121d50acf87db1c7","name":"Core i5-7360U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-7300","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i5 i5-7360u"],"fields":[{"key":"Model name","value":"Core i5-7360U","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-7360U","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR365","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-7300","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-03-20. 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Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. 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Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. 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Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. Not an independent measurement.","entityId":"cw-121d50acf87db1c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7360u&oldid=11799","sourceDate":"2019-03-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3791-r11799","location":"Intel/core i5/i5-7360u · revision 11799 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-20. 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Not an independent measurement.","entityId":"cw-123a0a125b7d901c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7235&oldid=8772","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"64x32 KiB","unit":"","sourceId":"chipswiki-2546-r8772","location":"Intel/xeon phi/7235 · revision 8772 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-123a0a125b7d901c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7235&oldid=8772","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2546-r8772","location":"Intel/xeon phi/7235 · revision 8772 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-123a0a125b7d901c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7235&oldid=8772","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"MiB","sourceId":"chipswiki-2546-r8772","location":"Intel/xeon phi/7235 · revision 8772 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-123a0a125b7d901c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7235&oldid=8772","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32x1 MiB","unit":"","sourceId":"chipswiki-2546-r8772","location":"Intel/xeon phi/7235 · revision 8772 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-123a0a125b7d901c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7235&oldid=8772","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2546-r8772","location":"Intel/xeon phi/7235 · revision 8772 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-123a0a125b7d901c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7235&oldid=8772","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-2546-r8772","location":"Intel/xeon phi/7235 · revision 8772 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-123a0a125b7d901c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7235&oldid=8772","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2546-r8772","location":"Intel/xeon phi/7235 · revision 8772 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-123a0a125b7d901c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7235&oldid=8772","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2546-r8772","location":"Intel/xeon phi/7235 · revision 8772 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-123a0a125b7d901c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7235&oldid=8772","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2546-r8772","location":"Intel/xeon phi/7235 · revision 8772 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-123a0a125b7d901c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7235&oldid=8772","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":95.35,"unit":"GiB/s","sourceId":"chipswiki-2546-r8772","location":"Intel/xeon phi/7235 · revision 8772 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-10. Not an independent measurement.","entityId":"cw-123a0a125b7d901c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20phi%2F7235&oldid=8772","sourceDate":"2019-05-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2546-r8772"],"url":"https://museum.vlsi.kr/objects/cw-123a0a125b7d901c"},{"id":"cw-12402b73da087e87","name":"Embedded G-Series T56N","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"G-Series APU/CPU","year":2011,"architecture":"Bobcat","process":"40 nm","aliases":["Amd embedded t56n"],"fields":[{"key":"Model name","value":"Embedded G-Series T56N","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"T56N","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GET56NGBB22GVE","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 19, 2011","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Embedded G-Series","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G-Series APU/CPU","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1650,"unit":"MHz","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1815,"unit":"MHz","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bobcat","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"eBrazos","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":20,"unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":451000000,"unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":75,"unit":"mm²","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2 × 512 KiB","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"10.67 GB/s","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon HD 6320","unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-414-r886","location":"Amd/embedded/t56n · revision 886 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56n&oldid=886","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FT1","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. 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Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":413,"unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.8-1.0 mm","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.92,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-12402b73da087e87","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-414-r886","chipswiki-31122-r91589"],"url":"https://museum.vlsi.kr/objects/cw-12402b73da087e87"},{"id":"cw-127ed6448cd4dee9","name":"Xeon E5-2689A v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2689a v4"],"fields":[{"key":"Model name","value":"Xeon E5-2689A v4","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2689A v4","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3400,"unit":"MHz","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2KZ","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":145,"unit":"W","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-127ed6448cd4dee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2689a%20v4&oldid=25098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7723-r25098","location":"Intel/xeon e5/e5-2689a v4 · revision 25098 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-3940XM","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AW8063801103501","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August, 2012","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 30, 2012","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-3000","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0US","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ivy Bridge","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Panther Point","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ivy Bridge","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"E1","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":55,"unit":"W","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"FCPGA988","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7826-r25286","location":"Intel/core i7ee/i7-3940xm · revision 25286 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1281f3e3357be035","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3940xm&oldid=25286","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7826-r25286"],"url":"https://museum.vlsi.kr/objects/cw-1281f3e3357be035"},{"id":"cw-12bf0e96f523281a","name":"Celeron G4900T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel celeron g4900t"],"fields":[{"key":"Model name","value":"Celeron G4900T","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4900T","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403379312","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3YP","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":88,"unit":"°C","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 610","unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6447-r20182","location":"Intel/celeron/g4900t · revision 20182 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-12bf0e96f523281a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4900t&oldid=20182","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6447-r20182"],"url":"https://museum.vlsi.kr/objects/cw-12bf0e96f523281a"},{"id":"cw-12c6c6f76642d730","name":"Am186ES–33KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ES","year":1995,"architecture":"80186","aliases":["Amd am186ex am186es–33kc\\w"],"fields":[{"key":"Model name","value":"Am186ES–33KC\\W","unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ES–33KC\\W","unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ES–33KC\\W","unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ES","unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"8.25 MT/s","unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14621-r44682","location":"Amd/am186ex/am186es–33kc\\w · revision 44682 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-12c6c6f76642d730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9333kc%5Cw&oldid=44682","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14621-r44682"],"url":"https://museum.vlsi.kr/objects/cw-12c6c6f76642d730"},{"id":"cw-12e447f847d08e29","name":"Core i5-7Y57","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-7Y","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i5 i5-7y57"],"fields":[{"key":"Model name","value":"Core i5-7Y57","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-7Y57","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8067702739527","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR33Y","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-7Y","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake Y","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 615","unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-4975-r16097","location":"Intel/core i5/i5-7y57 · revision 16097 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-12e447f847d08e29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7y57&oldid=16097","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4975-r16097"],"url":"https://museum.vlsi.kr/objects/cw-12e447f847d08e29"},{"id":"cw-12ec86b326824cb7","name":"EPYC 7551P","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7000","year":2017,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc 7551p"],"fields":[{"key":"Model name","value":"EPYC 7551P","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7551P","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PS755PBDVIHAF","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7000,"unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Naples","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":19200000000,"unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":180,"unit":"W","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":3,"unit":"MiB","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32x64 KiB","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32x512 KiB","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x8 MiB","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-5076-r16550","location":"Amd/epyc/7551p · revision 16550 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551p&oldid=16550","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-4094","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket SP3","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-12ec86b326824cb7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5076-r16550","chipswiki-31468-r92417"],"url":"https://museum.vlsi.kr/objects/cw-12ec86b326824cb7"},{"id":"cw-1342ebdef8bf4a2e","name":"Xeon D-2146NT","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-2000","year":2018,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon d d-2146nt"],"fields":[{"key":"Model name","value":"Xeon D-2146NT","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-2146NT","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8067303782601","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3ZR","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-2000","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DE","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M1","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":80,"unit":"W","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":11,"unit":"MiB","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.375 MiB","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-7150-r22571","location":"Intel/xeon d/d-2146nt · revision 22571 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2146nt&oldid=22571","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-2518","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":2518,"unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":52.5,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-1342ebdef8bf4a2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7150-r22571","chipswiki-31304-r92006"],"url":"https://museum.vlsi.kr/objects/cw-1342ebdef8bf4a2e"},{"id":"cw-13520fe9aa340aa6","name":"Xeon Gold 6148F","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6148f"],"fields":[{"key":"Model name","value":"Xeon Gold 6148F","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6148F","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303593800","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3KJ","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":160,"unit":"W","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":640,"unit":"KiB","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":20,"unit":"MiB","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x1 MiB","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":27.5,"unit":"MiB","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"20x1.375 MiB","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1497-r4949","location":"Intel/xeon gold/6148f · revision 4949 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-13520fe9aa340aa6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148f&oldid=4949","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1497-r4949"],"url":"https://museum.vlsi.kr/objects/cw-13520fe9aa340aa6"},{"id":"cw-1352c34b4127fdce","name":"Celeron 887E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron 887e"],"fields":[{"key":"Model name","value":"Celeron 887E","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"887E","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701082200","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0BV","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September, 2012","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 2012","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6933-r21620","location":"Intel/celeron/887e · revision 21620 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F887e&oldid=21620","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-1352c34b4127fdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6933-r21620","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-1352c34b4127fdce"},{"id":"cw-1360b1b763c5b3c0","name":"Core M 5Y31","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel core m 5y31"],"fields":[{"key":"Model name","value":"Core M 5Y31","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5Y31","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8065802061902","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2014","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2015","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core M","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2.4,"unit":"GHz","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR23G","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell Y","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"3D","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"MiB","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7814-r25263","location":"Intel/core m/5y31 · revision 25263 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1360b1b763c5b3c0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y31&oldid=25263","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7814-r25263"],"url":"https://museum.vlsi.kr/objects/cw-1360b1b763c5b3c0"},{"id":"cw-138be24a487adb6b","name":"Alchemy Au1550-333MBD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2004,"architecture":"Au1","aliases":["Alchemy au1550-333mbd"],"fields":[{"key":"Model name","value":"Alchemy Au1550-333MBD","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1550-333MBD","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1550-333MBDAA","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2004","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 2004","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AA","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1350 mW","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-166","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.332 GB/s","unit":"","sourceId":"chipswiki-466-r947","location":"Alchemy/au1550-333mbd · revision 947 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-138be24a487adb6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-333mbd&oldid=947","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-466-r947"],"url":"https://museum.vlsi.kr/objects/cw-138be24a487adb6b"},{"id":"cw-138e2c8d88a67603","name":"Core i5-7300HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-7300","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i5 i5-7300hq"],"fields":[{"key":"Model name","value":"Core i5-7300HQ","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-7300HQ","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR32S","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-7300","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-2176-r7309","location":"Intel/core i5/i5-7300hq · revision 7309 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300hq&oldid=7309","sourceDate":"2019-07-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-11. Not an independent measurement.","entityId":"cw-138e2c8d88a67603","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2176-r7309","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-138e2c8d88a67603"},{"id":"cw-13b30465fa0e664a","name":"EPYC 7H12","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7h12"],"fields":[{"key":"Model name","value":"EPYC 7H12","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7H12","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000055","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000055WOF","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 18, 2019","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 18, 2019","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. 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Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. 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Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. 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Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":64,"unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":128,"unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":280,"unit":"W","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4,"unit":"MiB","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"64x32 KiB","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"MiB","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"64x32 KiB","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"MiB","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"64x512 KiB","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x16 MiB","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-870-r2254","location":"Amd/epyc/7h12 · revision 2254 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-13b30465fa0e664a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7h12&oldid=2254","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-870-r2254"],"url":"https://museum.vlsi.kr/objects/cw-13b30465fa0e664a"},{"id":"cw-13c14381fc22e310","name":"Am486DX2-80NV8T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2V","year":1995,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx2-80nv8t"],"fields":[{"key":"Model name","value":"Am486DX2-80NV8T","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX2-80NV8T","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-80NV8T","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 1995","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2V","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":80,"unit":"MHz","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"40 MT/s","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX2V","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c14381fc22e310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-80nv8t&oldid=26758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8562-r26758","location":"Amd/am486/am486dx2-80nv8t · revision 26758 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6250","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 17, 2002","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 2003","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":146,"unit":"MHz","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM9","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM926EJ-S","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. 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Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CSP-409","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CSP","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. 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Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. 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Not an independent measurement.","entityId":"cw-13c2736f8483474f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6250&oldid=2141","sourceDate":"2021-02-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-829-r2141","location":"Qualcomm/msm6xxx/msm6250 · revision 2141 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-02. 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Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"x3-C3230RK","unit":"","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 4, 2015","unit":"","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 4, 2015","unit":"","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom x3","unit":"","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"C3000","unit":"","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Silvermont","unit":"","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"SoFIA","unit":"","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"SoFIA","unit":"","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-8048-r25684","location":"Intel/atom x3/x3-c3230rk · revision 25684 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c3a2a47438f63f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x3%2Fx3-c3230rk&oldid=25684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8048-r25684"],"url":"https://museum.vlsi.kr/objects/cw-13c3a2a47438f63f"},{"id":"cw-13c4cae9d1ada062","name":"AMD-K6-III/400AHX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III Desktop","year":1999,"architecture":"K6-III","process":"0.25 µm","aliases":["Amd k6-iii amd-k6-iii-400ahx"],"fields":[{"key":"Model name","value":"AMD-K6-III/400AHX","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-III/400AHX","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-III/400AHX","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 26, 1999","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 26, 1999","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III Desktop","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.99,"unit":"MHz","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sharptooth","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":9,"unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21300000,"unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":118,"unit":"mm²","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.4,"unit":"V","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8302-r25991","location":"Amd/k6-iii/amd-k6-iii-400ahx · revision 25991 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13c4cae9d1ada062","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400ahx&oldid=25991","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8302-r25991"],"url":"https://museum.vlsi.kr/objects/cw-13c4cae9d1ada062"},{"id":"cw-13c8cb586892a17e","name":"EPYC 7551","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7001","year":2017,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc 7551"],"fields":[{"key":"Model name","value":"EPYC 7551","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7551,"unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PS7551BDVIHAF","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7001,"unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Naples","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":19200000000,"unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":180,"unit":"W","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":3,"unit":"MiB","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32x64 KiB","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32x512 KiB","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x8 MiB","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-503-r1001","location":"Amd/epyc/7551 · revision 1001 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7551&oldid=1001","sourceDate":"2022-02-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-4094","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket SP3","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-25. Not an independent measurement.","entityId":"cw-13c8cb586892a17e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-503-r1001","chipswiki-31468-r92417"],"url":"https://museum.vlsi.kr/objects/cw-13c8cb586892a17e"},{"id":"cw-13d4e5f404284fc6","name":"Xeon E3-1535M v6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1500","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel xeon e3 e3-1535m v6"],"fields":[{"key":"Model name","value":"Xeon E3-1535M v6","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1535M v6","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR32H","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1500","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. 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Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics P630","unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6408-r20007","location":"Intel/xeon e3/e3-1535m v6 · revision 20007 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1535m%20v6&oldid=20007","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-13d4e5f404284fc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6408-r20007","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-13d4e5f404284fc6"},{"id":"cw-13e64486dd257350","name":"CN3630-500 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3600","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3630-500bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN3630-500 EXP","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3630-500 EXP","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3630-500BG1521-EXP","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August, 2005","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2005","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3600","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":5.96,"unit":"GiB/s","sourceId":"chipswiki-8235-r25894","location":"Cavium/octeon/cn3630-500bg1521-exp · revision 25894 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3630-500bg1521-exp&oldid=25894","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-13e64486dd257350","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8235-r25894","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-13e64486dd257350"},{"id":"cw-14bbc91927dfdee9","name":"8008","kind":"sku","entityType":"product-model","subtype":"sku","company":"Intel","year":null,"architecture":"8008","process":"10 μm","aliases":["Intel mcs-8 8008"],"fields":[{"key":"Model name","value":8008,"unit":"","sourceId":"chipswiki-428-r904","location":"Intel/mcs-8/8008 · revision 904 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-23. Not an independent measurement.","entityId":"cw-14bbc91927dfdee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008&oldid=904","sourceDate":"2022-03-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-428-r904","location":"Intel/mcs-8/8008 · revision 904 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-23. Not an independent measurement.","entityId":"cw-14bbc91927dfdee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008&oldid=904","sourceDate":"2022-03-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-428-r904","location":"Intel/mcs-8/8008 · revision 904 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-23. Not an independent measurement.","entityId":"cw-14bbc91927dfdee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008&oldid=904","sourceDate":"2022-03-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8008,"unit":"","sourceId":"chipswiki-428-r904","location":"Intel/mcs-8/8008 · revision 904 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-23. Not an independent measurement.","entityId":"cw-14bbc91927dfdee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008&oldid=904","sourceDate":"2022-03-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":8008,"unit":"","sourceId":"chipswiki-428-r904","location":"Intel/mcs-8/8008 · revision 904 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-23. Not an independent measurement.","entityId":"cw-14bbc91927dfdee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008&oldid=904","sourceDate":"2022-03-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April, 1972","unit":"","sourceId":"chipswiki-428-r904","location":"Intel/mcs-8/8008 · revision 904 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-23. Not an independent measurement.","entityId":"cw-14bbc91927dfdee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008&oldid=904","sourceDate":"2022-03-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MCS-8","unit":"","sourceId":"chipswiki-428-r904","location":"Intel/mcs-8/8008 · revision 904 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-23. Not an independent measurement.","entityId":"cw-14bbc91927dfdee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008&oldid=904","sourceDate":"2022-03-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"kHz","sourceId":"chipswiki-428-r904","location":"Intel/mcs-8/8008 · revision 904 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-23. Not an independent measurement.","entityId":"cw-14bbc91927dfdee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008&oldid=904","sourceDate":"2022-03-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8008,"unit":"","sourceId":"chipswiki-428-r904","location":"Intel/mcs-8/8008 · revision 904 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-23. Not an independent measurement.","entityId":"cw-14bbc91927dfdee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008&oldid=904","sourceDate":"2022-03-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"10 μm","unit":"","sourceId":"chipswiki-428-r904","location":"Intel/mcs-8/8008 · revision 904 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-23. Not an independent measurement.","entityId":"cw-14bbc91927dfdee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008&oldid=904","sourceDate":"2022-03-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3500,"unit":"","sourceId":"chipswiki-428-r904","location":"Intel/mcs-8/8008 · revision 904 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-23. Not an independent measurement.","entityId":"cw-14bbc91927dfdee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008&oldid=904","sourceDate":"2022-03-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"pMOS","unit":"","sourceId":"chipswiki-428-r904","location":"Intel/mcs-8/8008 · revision 904 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-23. Not an independent measurement.","entityId":"cw-14bbc91927dfdee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008&oldid=904","sourceDate":"2022-03-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-428-r904","location":"Intel/mcs-8/8008 · revision 904 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-23. Not an independent measurement.","entityId":"cw-14bbc91927dfdee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008&oldid=904","sourceDate":"2022-03-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"KiB","sourceId":"chipswiki-428-r904","location":"Intel/mcs-8/8008 · revision 904 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-23. Not an independent measurement.","entityId":"cw-14bbc91927dfdee9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-8%2F8008&oldid=904","sourceDate":"2022-03-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-428-r904"],"url":"https://museum.vlsi.kr/objects/cw-14bbc91927dfdee9"},{"id":"cw-14dab42461438f4e","name":"Ryzen 5 PRO 4650U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 5 pro 4650u"],"fields":[{"key":"Model name","value":"Ryzen 5 PRO 4650U","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 4650U","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000103","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 7, 2020","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 7, 2020","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"68.27 GB/s","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1500,"unit":"MHz","sourceId":"chipswiki-693-r1688","location":"Amd/ryzen 5/pro 4650u · revision 1688 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-14dab42461438f4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650u&oldid=1688","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-693-r1688"],"url":"https://museum.vlsi.kr/objects/cw-14dab42461438f4e"},{"id":"cw-14f0fe562a4a1798","name":"Joshua","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Cyrix","year":null,"process":"0.18 µm","aliases":["Cyrix microarchitectures joshua"],"fields":[{"key":"Architecture name","value":"Joshua","unit":"","sourceId":"chipswiki-7328-r23631","location":"Cyrix/microarchitectures/joshua · revision 23631 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-20. Not an independent measurement.","entityId":"cw-14f0fe562a4a1798","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cyrix%2Fmicroarchitectures%2Fjoshua&oldid=23631","sourceDate":"2018-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cyrix","unit":"","sourceId":"chipswiki-7328-r23631","location":"Cyrix/microarchitectures/joshua · revision 23631 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-20. Not an independent measurement.","entityId":"cw-14f0fe562a4a1798","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cyrix%2Fmicroarchitectures%2Fjoshua&oldid=23631","sourceDate":"2018-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Texas Instruments","unit":"","sourceId":"chipswiki-7328-r23631","location":"Cyrix/microarchitectures/joshua · revision 23631 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-20. Not an independent measurement.","entityId":"cw-14f0fe562a4a1798","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cyrix%2Fmicroarchitectures%2Fjoshua&oldid=23631","sourceDate":"2018-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-7328-r23631","location":"Cyrix/microarchitectures/joshua · revision 23631 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-20. Not an independent measurement.","entityId":"cw-14f0fe562a4a1798","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cyrix%2Fmicroarchitectures%2Fjoshua&oldid=23631","sourceDate":"2018-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-7328-r23631","location":"Cyrix/microarchitectures/joshua · revision 23631 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-20. Not an independent measurement.","entityId":"cw-14f0fe562a4a1798","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cyrix%2Fmicroarchitectures%2Fjoshua&oldid=23631","sourceDate":"2018-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":7,"unit":"","sourceId":"chipswiki-7328-r23631","location":"Cyrix/microarchitectures/joshua · revision 23631 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-20. Not an independent measurement.","entityId":"cw-14f0fe562a4a1798","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cyrix%2Fmicroarchitectures%2Fjoshua&oldid=23631","sourceDate":"2018-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-7328-r23631","location":"Cyrix/microarchitectures/joshua · revision 23631 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-20. Not an independent measurement.","entityId":"cw-14f0fe562a4a1798","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cyrix%2Fmicroarchitectures%2Fjoshua&oldid=23631","sourceDate":"2018-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cayenne","unit":"","sourceId":"chipswiki-7328-r23631","location":"Cyrix/microarchitectures/joshua · revision 23631 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-20. Not an independent measurement.","entityId":"cw-14f0fe562a4a1798","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cyrix%2Fmicroarchitectures%2Fjoshua&oldid=23631","sourceDate":"2018-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Samuel","unit":"","sourceId":"chipswiki-7328-r23631","location":"Cyrix/microarchitectures/joshua · revision 23631 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-20. Not an independent measurement.","entityId":"cw-14f0fe562a4a1798","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cyrix%2Fmicroarchitectures%2Fjoshua&oldid=23631","sourceDate":"2018-01-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7328-r23631"],"url":"https://museum.vlsi.kr/objects/cw-14f0fe562a4a1798"},{"id":"cw-15061533bff06183","name":"Atom Z615","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z615","year":2010,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z615"],"fields":[{"key":"Model name","value":"Atom Z615","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z615","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AY80609005802AA","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBZL","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 4, 2010","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 4, 2010","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z615","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1600,"unit":"MHz","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"cDMI","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"400 MT/s","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Moorestown","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Langwell","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Lincroft","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":38,"unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":140000000,"unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":65.2526,"unit":"mm²","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2.2,"unit":"W","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":2.98,"unit":"GiB/s","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX535","unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":1,"unit":"","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8055-r25691","location":"Intel/atom/z615 · revision 25691 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz615&oldid=25691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-518","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":518,"unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.1,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15061533bff06183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8055-r25691","chipswiki-31501-r92563"],"url":"https://museum.vlsi.kr/objects/cw-15061533bff06183"},{"id":"cw-1517ec1e803762a9","name":"Atom C3558","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Goldmont","process":"14 nm","aliases":["Intel atom c3558"],"fields":[{"key":"Model name","value":"Atom C3558","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C3558","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HW8076502639302","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR388","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":95,"unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":16,"unit":"W","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":224,"unit":"KiB","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-1866","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.82,"unit":"GiB/s","sourceId":"chipswiki-1861-r6396","location":"Intel/atom/c3558 · revision 6396 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3558&oldid=6396","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1310","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1310,"unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-1517ec1e803762a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1861-r6396","chipswiki-31416-r92275"],"url":"https://museum.vlsi.kr/objects/cw-1517ec1e803762a9"},{"id":"cw-1521a3573ec1d9f5","name":"Core i7-8559U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i7 i7-8559u"],"fields":[{"key":"Model name","value":"Core i7-8559U","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-8559U","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8068403419332","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRCK5","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-8000","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4500,"unit":"MHz","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake U","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D0","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":28,"unit":"W","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Plus Graphics 655","unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-5284-r17289","location":"Intel/core i7/i7-8559u · revision 17289 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8559u&oldid=17289","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1528","unit":"","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1528,"unit":"","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":46,"unit":"mm","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-1521a3573ec1d9f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5284-r17289","chipswiki-31288-r91954"],"url":"https://museum.vlsi.kr/objects/cw-1521a3573ec1d9f5"},{"id":"cw-154d6ee6341d8b4f","name":"Core i7-6600U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-6600u"],"fields":[{"key":"Model name","value":"Core i7-6600U","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6600U","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066201924950","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2F1","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. 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Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. Not an independent measurement.","entityId":"cw-154d6ee6341d8b4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6600u&oldid=21443","sourceDate":"2018-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6873-r21443","location":"Intel/core i7/i7-6600u · revision 21443 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-26. 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Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 1987","unit":"","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"R80286","unit":"","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":16,"unit":"MHz","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"16 MT/s","unit":"","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":134000,"unit":"","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":73,"unit":"mm²","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CLCC-68","unit":"","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CLCC","unit":"","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CLCC-68","unit":"","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8583-r26781","location":"Amd/am286/r80286-16 · revision 26781 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-155dac3f5f3e5398","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fr80286-16&oldid=26781","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8583-r26781"],"url":"https://museum.vlsi.kr/objects/cw-155dac3f5f3e5398"},{"id":"cw-1576d6810e53a3af","name":"Core i7-2760QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2760qm"],"fields":[{"key":"Model name","value":"Core i7-2760QM","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2760QM","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062701065300","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701065400","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR02W","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR02R","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":216,"unit":"mm²","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":23.84,"unit":"GiB/s","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1576d6810e53a3af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7875-r25379","location":"Intel/core i7/i7-2760qm · revision 25379 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x8 KiB","unit":"","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8246-r25906","location":"Cavium/octeon/cn3120-400bg868-scp · revision 25906 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-scp&oldid=25906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-15df0d6c86c71668","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8246-r25906","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-15df0d6c86c71668"},{"id":"cw-15e7e3792ceb22cd","name":"Atom C3338","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Goldmont","process":"14 nm","aliases":["Intel atom c3338"],"fields":[{"key":"Model name","value":"Atom C3338","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C3338","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HW8076502639602","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR36E","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR38B","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 22, 2017","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 22, 2017","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":95,"unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":9,"unit":"W","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":112,"unit":"KiB","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":48,"unit":"KiB","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x24 KiB","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-1866","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-1860-r6394","location":"Intel/atom/c3338 · revision 6394 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3338&oldid=6394","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1310","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1310,"unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-15e7e3792ceb22cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1860-r6394","chipswiki-31416-r92275"],"url":"https://museum.vlsi.kr/objects/cw-15e7e3792ceb22cd"},{"id":"cw-161971e1262436b4","name":"Am486DX2-100V8T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2V","year":1994,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx2-100v8t"],"fields":[{"key":"Model name","value":"Am486DX2-100V8T","unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX2-100V8T","unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-100V8T","unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1994,"unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2V","unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":100,"unit":"MHz","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"50 MT/s","unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX2V","unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8569-r26767","location":"Amd/am486/am486dx2-100v8t · revision 26767 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-161971e1262436b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100v8t&oldid=26767","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8569-r26767"],"url":"https://museum.vlsi.kr/objects/cw-161971e1262436b4"},{"id":"cw-162a8f9cf03f33da","name":"Exynos 9820","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 9","year":2019,"architecture":"Exynos M4","process":"8 nm","aliases":["Samsung exynos 9820"],"fields":[{"key":"Model name","value":"Exynos 9820","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":9820,"unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 14, 2018","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2019","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 9","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Exynos M4","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cheetah","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A75","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A55","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":8,"unit":"nm","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":127,"unit":"mm²","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":12,"unit":"GiB","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":192,"unit":"KiB","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":128,"unit":"KiB","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"2x64 KiB","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 1)","value":"4-way set associative","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":64,"unit":"KiB","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"2x32 KiB","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 1)","value":"8-way set associative","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":1,"unit":"MiB","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"2x512 KiB","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 1)","value":"16-way set associative","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache — Cache (section 1)","value":2,"unit":"MiB","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization — Cache (section 1)","value":"2x1 MiB","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":256,"unit":"KiB","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 2)","value":"2x64 KiB","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 2)","value":"4-way set associative","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 2)","value":"2x64 KiB","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 2)","value":"16-way set associative","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":512,"unit":"KiB","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"2x256 KiB","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 2)","value":"8-way set associative","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3600","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. 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Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G76","unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. 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Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":702,"unit":"MHz","sourceId":"chipswiki-770-r1889","location":"Samsung/exynos/9820 · revision 1889 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-28. Not an independent measurement.","entityId":"cw-162a8f9cf03f33da","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9820&oldid=1889","sourceDate":"2021-04-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-770-r1889"],"url":"https://museum.vlsi.kr/objects/cw-162a8f9cf03f33da"},{"id":"cw-16401268ea46582c","name":"Pentium P6200","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P6000","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel pentium (2009) p6200"],"fields":[{"key":"Model name","value":"Intel Pentium P6200","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P6200","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617004122AW","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 26, 2010","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 26, 2010","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P6000","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2133.33,"unit":"MHz","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBUA","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-16401268ea46582c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6200&oldid=25209","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7778-r25209","location":"Intel/pentium (2009)/p6200 · revision 25209 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8247-r25907","location":"Cavium/octeon/cn3120-400bg868-nsp · revision 25907 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8247-r25907","location":"Cavium/octeon/cn3120-400bg868-nsp · revision 25907 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8247-r25907","location":"Cavium/octeon/cn3120-400bg868-nsp · revision 25907 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8247-r25907","location":"Cavium/octeon/cn3120-400bg868-nsp · revision 25907 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":80,"unit":"KiB","sourceId":"chipswiki-8247-r25907","location":"Cavium/octeon/cn3120-400bg868-nsp · revision 25907 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8247-r25907","location":"Cavium/octeon/cn3120-400bg868-nsp · revision 25907 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8247-r25907","location":"Cavium/octeon/cn3120-400bg868-nsp · revision 25907 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8247-r25907","location":"Cavium/octeon/cn3120-400bg868-nsp · revision 25907 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-8247-r25907","location":"Cavium/octeon/cn3120-400bg868-nsp · revision 25907 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x8 KiB","unit":"","sourceId":"chipswiki-8247-r25907","location":"Cavium/octeon/cn3120-400bg868-nsp · revision 25907 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8247-r25907","location":"Cavium/octeon/cn3120-400bg868-nsp · revision 25907 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8247-r25907","location":"Cavium/octeon/cn3120-400bg868-nsp · revision 25907 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8247-r25907","location":"Cavium/octeon/cn3120-400bg868-nsp · revision 25907 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8247-r25907","location":"Cavium/octeon/cn3120-400bg868-nsp · revision 25907 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8247-r25907","location":"Cavium/octeon/cn3120-400bg868-nsp · revision 25907 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-400bg868-nsp&oldid=25907","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1684de4e02f4909f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8247-r25907","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-1684de4e02f4909f"},{"id":"cw-1692b9ffc5390fb8","name":"Polaris","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2007,"process":"65 nm","aliases":["Intel microarchitectures polaris"],"fields":[{"key":"Architecture name","value":"Polaris","unit":"","sourceId":"chipswiki-2503-r8586","location":"Intel/microarchitectures/polaris · revision 8586 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. 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Not an independent measurement.","entityId":"cw-1692b9ffc5390fb8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpolaris&oldid=8586","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2503-r8586","location":"Intel/microarchitectures/polaris · revision 8586 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-1692b9ffc5390fb8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpolaris&oldid=8586","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"February 2007","unit":"","sourceId":"chipswiki-2503-r8586","location":"Intel/microarchitectures/polaris · revision 8586 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. 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Not an independent measurement.","entityId":"cw-1692b9ffc5390fb8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpolaris&oldid=8586","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":80,"unit":"","sourceId":"chipswiki-2503-r8586","location":"Intel/microarchitectures/polaris · revision 8586 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-1692b9ffc5390fb8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpolaris&oldid=8586","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"VLIW","unit":"","sourceId":"chipswiki-2503-r8586","location":"Intel/microarchitectures/polaris · revision 8586 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-1692b9ffc5390fb8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpolaris&oldid=8586","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":9,"unit":"","sourceId":"chipswiki-2503-r8586","location":"Intel/microarchitectures/polaris · revision 8586 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-1692b9ffc5390fb8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpolaris&oldid=8586","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Rock Creek","unit":"","sourceId":"chipswiki-2503-r8586","location":"Intel/microarchitectures/polaris · revision 8586 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-1692b9ffc5390fb8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpolaris&oldid=8586","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Larrabee","unit":"","sourceId":"chipswiki-2503-r8586","location":"Intel/microarchitectures/polaris · revision 8586 · {{microarchitecture}} / successor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 2","note":"Source-reported parameter; source revision 2019-05-18. Not an independent measurement.","entityId":"cw-1692b9ffc5390fb8","scope":"successor 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpolaris&oldid=8586","sourceDate":"2019-05-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2503-r8586"],"url":"https://museum.vlsi.kr/objects/cw-1692b9ffc5390fb8"},{"id":"cw-16a68ddbea7e1e85","name":"EPYC 7302","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7302"],"fields":[{"key":"Model name","value":"EPYC 7302","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7302,"unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000043","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000043WOF","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":155,"unit":"W","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x512 KiB","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x16 MiB","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-856-r2236","location":"Amd/epyc/7302 · revision 2236 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-16a68ddbea7e1e85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302&oldid=2236","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-856-r2236"],"url":"https://museum.vlsi.kr/objects/cw-16a68ddbea7e1e85"},{"id":"cw-172c166596c975c5","name":"Xeon Silver 4214R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4200","year":2020,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon silver 4214r"],"fields":[{"key":"Model name","value":"Xeon Silver 4214R","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4214R","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4200,"unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake R","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":100,"unit":"W","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x1 MiB","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16.5,"unit":"MiB","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.375 MiB","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1171-r3649","location":"Intel/xeon silver/4214r · revision 3649 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-172c166596c975c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214r&oldid=3649","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1171-r3649"],"url":"https://museum.vlsi.kr/objects/cw-172c166596c975c5"},{"id":"cw-172fb7de295a5edd","name":"Matrix-2000","kind":"sku","entityType":"product-model","subtype":"cpu","company":"NUDT","year":2017,"aliases":["Nudt matrix-2000"],"fields":[{"key":"Model name","value":"Matrix-2000","unit":"","sourceId":"chipswiki-2169-r7265","location":"Nudt/matrix-2000 · revision 7265 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-19. Not an independent measurement.","entityId":"cw-172fb7de295a5edd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nudt%2Fmatrix-2000&oldid=7265","sourceDate":"2019-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"NUDT","unit":"","sourceId":"chipswiki-2169-r7265","location":"Nudt/matrix-2000 · revision 7265 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-19. Not an independent measurement.","entityId":"cw-172fb7de295a5edd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nudt%2Fmatrix-2000&oldid=7265","sourceDate":"2019-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Matrix-2000","unit":"","sourceId":"chipswiki-2169-r7265","location":"Nudt/matrix-2000 · revision 7265 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-19. Not an independent measurement.","entityId":"cw-172fb7de295a5edd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nudt%2Fmatrix-2000&oldid=7265","sourceDate":"2019-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2015,"unit":"","sourceId":"chipswiki-2169-r7265","location":"Nudt/matrix-2000 · revision 7265 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-19. Not an independent measurement.","entityId":"cw-172fb7de295a5edd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nudt%2Fmatrix-2000&oldid=7265","sourceDate":"2019-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2017,"unit":"","sourceId":"chipswiki-2169-r7265","location":"Nudt/matrix-2000 · revision 7265 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-19. Not an independent measurement.","entityId":"cw-172fb7de295a5edd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nudt%2Fmatrix-2000&oldid=7265","sourceDate":"2019-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-2169-r7265","location":"Nudt/matrix-2000 · revision 7265 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-19. Not an independent measurement.","entityId":"cw-172fb7de295a5edd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nudt%2Fmatrix-2000&oldid=7265","sourceDate":"2019-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2169-r7265","location":"Nudt/matrix-2000 · revision 7265 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-19. Not an independent measurement.","entityId":"cw-172fb7de295a5edd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nudt%2Fmatrix-2000&oldid=7265","sourceDate":"2019-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2169-r7265","location":"Nudt/matrix-2000 · revision 7265 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-19. 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Not an independent measurement.","entityId":"cw-172fb7de295a5edd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nudt%2Fmatrix-2000&oldid=7265","sourceDate":"2019-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":128,"unit":"","sourceId":"chipswiki-2169-r7265","location":"Nudt/matrix-2000 · revision 7265 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-19. Not an independent measurement.","entityId":"cw-172fb7de295a5edd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nudt%2Fmatrix-2000&oldid=7265","sourceDate":"2019-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2169-r7265","location":"Nudt/matrix-2000 · revision 7265 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-19. Not an independent measurement.","entityId":"cw-172fb7de295a5edd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nudt%2Fmatrix-2000&oldid=7265","sourceDate":"2019-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2169-r7265","location":"Nudt/matrix-2000 · revision 7265 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-19. Not an independent measurement.","entityId":"cw-172fb7de295a5edd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nudt%2Fmatrix-2000&oldid=7265","sourceDate":"2019-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-2169-r7265","location":"Nudt/matrix-2000 · revision 7265 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-19. Not an independent measurement.","entityId":"cw-172fb7de295a5edd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nudt%2Fmatrix-2000&oldid=7265","sourceDate":"2019-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-2169-r7265","location":"Nudt/matrix-2000 · revision 7265 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-19. Not an independent measurement.","entityId":"cw-172fb7de295a5edd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nudt%2Fmatrix-2000&oldid=7265","sourceDate":"2019-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":143.1,"unit":"GiB/s","sourceId":"chipswiki-2169-r7265","location":"Nudt/matrix-2000 · revision 7265 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-19. Not an independent measurement.","entityId":"cw-172fb7de295a5edd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nudt%2Fmatrix-2000&oldid=7265","sourceDate":"2019-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCCLGA-4201","unit":"","sourceId":"chipswiki-31387-r92191","location":"Template:Packages/nudt/fclga-4201 · revision 92191 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-19. 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Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":133,"unit":"MHz","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5x","unit":"","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1600000,"unit":"","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":43,"unit":"mm²","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SQFP-208","unit":"","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SQFP","unit":"","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-8525-r26720","location":"Amd/am5x86/amd-x5-133sfw · revision 26720 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-17bcac86574da7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfw&oldid=26720","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8525-r26720"],"url":"https://museum.vlsi.kr/objects/cw-17bcac86574da7b5"},{"id":"cw-17d8596a0814f231","name":"Celeron N3010","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N3000","year":2016,"architecture":"Airmont","process":"14 nm","aliases":["Intel celeron n3010"],"fields":[{"key":"Model name","value":"Intel Celeron N3010","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N3010","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066501715938","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2KM","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 10, 2016","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 10, 2016","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N3000","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1040,"unit":"MHz","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2240,"unit":"MHz","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"IDI","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Braswell","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4,"unit":"W","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA1170","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":48,"unit":"KiB","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x24 KiB","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-6863-r21417","location":"Intel/celeron/n3010 · revision 21417 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-17d8596a0814f231","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3010&oldid=21417","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6863-r21417"],"url":"https://museum.vlsi.kr/objects/cw-17d8596a0814f231"},{"id":"cw-17e7ddf495af1d1a","name":"Gen1","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":1998,"aliases":["Intel microarchitectures gen1"],"fields":[{"key":"Architecture name","value":"Gen1","unit":"","sourceId":"chipswiki-15961-r52689","location":"Intel/microarchitectures/gen1 · revision 52689 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-17e7ddf495af1d1a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen1&oldid=52689","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-15961-r52689","location":"Intel/microarchitectures/gen1 · revision 52689 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-17e7ddf495af1d1a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen1&oldid=52689","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-15961-r52689","location":"Intel/microarchitectures/gen1 · revision 52689 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-17e7ddf495af1d1a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen1&oldid=52689","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":1998,"unit":"","sourceId":"chipswiki-15961-r52689","location":"Intel/microarchitectures/gen1 · revision 52689 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-17e7ddf495af1d1a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen1&oldid=52689","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Pro-1000","unit":"","sourceId":"chipswiki-15961-r52689","location":"Intel/microarchitectures/gen1 · revision 52689 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-17e7ddf495af1d1a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen1&oldid=52689","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gen2","unit":"","sourceId":"chipswiki-15961-r52689","location":"Intel/microarchitectures/gen1 · revision 52689 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-17e7ddf495af1d1a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen1&oldid=52689","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-15961-r52689"],"url":"https://museum.vlsi.kr/objects/cw-17e7ddf495af1d1a"},{"id":"cw-17e962b0bec11774","name":"Jupiter Sound","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2022,"process":"10 nm","aliases":["Intel microarchitectures jupiter sound"],"fields":[{"key":"Architecture name","value":"Jupiter Sound","unit":"","sourceId":"chipswiki-6347-r19681","location":"Intel/microarchitectures/jupiter sound · revision 19681 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-30. 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Not an independent measurement.","entityId":"cw-17e962b0bec11774","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fjupiter%20sound&oldid=19681","sourceDate":"2018-04-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6347-r19681","location":"Intel/microarchitectures/jupiter sound · revision 19681 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-30. Not an independent measurement.","entityId":"cw-17e962b0bec11774","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fjupiter%20sound&oldid=19681","sourceDate":"2018-04-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2022,"unit":"","sourceId":"chipswiki-6347-r19681","location":"Intel/microarchitectures/jupiter sound · revision 19681 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-30. 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Not an independent measurement.","entityId":"cw-181f7dc1631ca83f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk7&oldid=994","sourceDate":"2022-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-498-r994","location":"Amd/microarchitectures/k7 · revision 994 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-03-03. 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Not an independent measurement.","entityId":"cw-181f7dc1631ca83f","scope":"core name 5","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk7&oldid=994","sourceDate":"2022-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Palomino","unit":"","sourceId":"chipswiki-498-r994","location":"Amd/microarchitectures/k7 · revision 994 · {{microarchitecture}} / core name 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 6","note":"Source-reported parameter; source revision 2022-03-03. Not an independent measurement.","entityId":"cw-181f7dc1631ca83f","scope":"core name 6","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk7&oldid=994","sourceDate":"2022-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Thoroughbred","unit":"","sourceId":"chipswiki-498-r994","location":"Amd/microarchitectures/k7 · revision 994 · {{microarchitecture}} / core name 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 7","note":"Source-reported parameter; source revision 2022-03-03. Not an independent measurement.","entityId":"cw-181f7dc1631ca83f","scope":"core name 7","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk7&oldid=994","sourceDate":"2022-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Barton","unit":"","sourceId":"chipswiki-498-r994","location":"Amd/microarchitectures/k7 · revision 994 · {{microarchitecture}} / core name 8","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 8","note":"Source-reported parameter; source revision 2022-03-03. Not an independent measurement.","entityId":"cw-181f7dc1631ca83f","scope":"core name 8","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk7&oldid=994","sourceDate":"2022-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"K6-III","unit":"","sourceId":"chipswiki-498-r994","location":"Amd/microarchitectures/k7 · revision 994 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-03. Not an independent measurement.","entityId":"cw-181f7dc1631ca83f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk7&oldid=994","sourceDate":"2022-03-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"K8","unit":"","sourceId":"chipswiki-498-r994","location":"Amd/microarchitectures/k7 · revision 994 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-03. Not an independent measurement.","entityId":"cw-181f7dc1631ca83f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk7&oldid=994","sourceDate":"2022-03-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-498-r994"],"url":"https://museum.vlsi.kr/objects/cw-181f7dc1631ca83f"},{"id":"cw-185df07a2d2a0bb9","name":"AMD-K6/266AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Desktop K6","year":1998,"architecture":"K6","process":"250 nm","aliases":["Amd k6 amd-k6 266afr"],"fields":[{"key":"Model name","value":"AMD-K6/266AFR","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6/266AFR","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6/266AFR","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 1998","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 5, 1998","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Desktop K6","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":266.66,"unit":"MHz","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Little Foot","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":68,"unit":"mm²","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8286-r25973","location":"Amd/k6/amd-k6/266afr · revision 25973 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-185df07a2d2a0bb9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266afr&oldid=25973","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8286-r25973"],"url":"https://museum.vlsi.kr/objects/cw-185df07a2d2a0bb9"},{"id":"cw-186ff29af555ae99","name":"Ryzen 3 5300G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 3 5300g"],"fields":[{"key":"Model name","value":"Ryzen 3 5300G","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5300G","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000253","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 13, 2021","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":4000,"unit":"MHz","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x8 MiB","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1700,"unit":"MHz","sourceId":"chipswiki-707-r1713","location":"Amd/ryzen 3/5300g · revision 1713 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-186ff29af555ae99","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F5300g&oldid=1713","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-707-r1713"],"url":"https://museum.vlsi.kr/objects/cw-186ff29af555ae99"},{"id":"cw-18945f06f9eee180","name":"CN3110-400 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-400bg868-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3110-400 NSP","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-400 NSP","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-400BG868-NSP","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-nsp&oldid=25923","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8263-r25923","location":"Cavium/octeon/cn3110-400bg868-nsp · revision 25923 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18945f06f9eee180","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8263-r25923","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-18945f06f9eee180"},{"id":"cw-18a2158720f807cf","name":"Core i7-2637M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2637m"],"fields":[{"key":"Model name","value":"Core i7-2637M","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2637M","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701041105","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0D3","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2011","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2011","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-7893-r25397","location":"Intel/core i7/i7-2637m · revision 25397 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-18a2158720f807cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7893-r25397","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-18a2158720f807cf"},{"id":"cw-18bc410a9d720e9b","name":"Celeron G3930TE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"G3900TE","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel celeron g3930te"],"fields":[{"key":"Model name","value":"Celeron G3930TE","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. 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Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G3930TE","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. 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Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR38H","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 12, 2017","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 12, 2017","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G3900TE","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":88,"unit":"°C","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 610","unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-6435-r20123","location":"Intel/celeron/g3930te · revision 20123 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-18bc410a9d720e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930te&oldid=20123","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6435-r20123"],"url":"https://museum.vlsi.kr/objects/cw-18bc410a9d720e9b"},{"id":"cw-18ec2fe1b38aa0fe","name":"Xeon Gold 6142","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6142"],"fields":[{"key":"Model name","value":"Xeon Gold 6142","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6142,"unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806736142","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303405400","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3AY","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1500-r4952","location":"Intel/xeon gold/6142 · revision 4952 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-18ec2fe1b38aa0fe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142&oldid=4952","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1500-r4952"],"url":"https://museum.vlsi.kr/objects/cw-18ec2fe1b38aa0fe"},{"id":"cw-1903f824abcc9459","name":"Core i3-330E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-300","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i3 i3-330e"],"fields":[{"key":"Model name","value":"Intel Core i3-330E","unit":"","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-330E","unit":"","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617004467AC","unit":"","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-300","unit":"","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2133.33,"unit":"MHz","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBQC","unit":"","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1903f824abcc9459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330e&oldid=25575","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7994-r25575","location":"Intel/core i3/i3-330e · revision 25575 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–33KC\\W","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ER–33KC\\W","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 1996","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1996","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"8.25 MT/s","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14644-r44705","location":"Amd/am186ex/am186er–33kc\\w · revision 44705 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-190d4f26a976709f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333kc%5Cw&oldid=44705","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14644-r44705"],"url":"https://museum.vlsi.kr/objects/cw-190d4f26a976709f"},{"id":"cw-19367ad2ef605e0b","name":"ZhangJiang","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Zhaoxin","year":2015,"process":"28 nm","aliases":["Zhaoxin microarchitectures zhangjiang"],"fields":[{"key":"Architecture name","value":"ZhangJiang","unit":"","sourceId":"chipswiki-604-r1410","location":"Zhaoxin/microarchitectures/zhangjiang · revision 1410 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-19367ad2ef605e0b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Fzhangjiang&oldid=1410","sourceDate":"2021-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Zhaoxin","unit":"","sourceId":"chipswiki-604-r1410","location":"Zhaoxin/microarchitectures/zhangjiang · revision 1410 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-19367ad2ef605e0b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Fzhangjiang&oldid=1410","sourceDate":"2021-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-604-r1410","location":"Zhaoxin/microarchitectures/zhangjiang · revision 1410 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-19367ad2ef605e0b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Fzhangjiang&oldid=1410","sourceDate":"2021-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2015,"unit":"","sourceId":"chipswiki-604-r1410","location":"Zhaoxin/microarchitectures/zhangjiang · revision 1410 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-19367ad2ef605e0b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Fzhangjiang&oldid=1410","sourceDate":"2021-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-604-r1410","location":"Zhaoxin/microarchitectures/zhangjiang · revision 1410 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-19367ad2ef605e0b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Fzhangjiang&oldid=1410","sourceDate":"2021-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-604-r1410","location":"Zhaoxin/microarchitectures/zhangjiang · revision 1410 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-19367ad2ef605e0b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Fzhangjiang&oldid=1410","sourceDate":"2021-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-604-r1410","location":"Zhaoxin/microarchitectures/zhangjiang · revision 1410 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-19367ad2ef605e0b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Fzhangjiang&oldid=1410","sourceDate":"2021-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-604-r1410","location":"Zhaoxin/microarchitectures/zhangjiang · revision 1410 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-19367ad2ef605e0b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Fzhangjiang&oldid=1410","sourceDate":"2021-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Isaiah II","unit":"","sourceId":"chipswiki-604-r1410","location":"Zhaoxin/microarchitectures/zhangjiang · revision 1410 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-19367ad2ef605e0b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Fzhangjiang&oldid=1410","sourceDate":"2021-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"WuDaoKou","unit":"","sourceId":"chipswiki-604-r1410","location":"Zhaoxin/microarchitectures/zhangjiang · revision 1410 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-19367ad2ef605e0b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fmicroarchitectures%2Fzhangjiang&oldid=1410","sourceDate":"2021-09-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-604-r1410"],"url":"https://museum.vlsi.kr/objects/cw-19367ad2ef605e0b"},{"id":"cw-1942c7146ed1b70d","name":"Core i7-7820EQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-7800","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i7 i7-7820eq"],"fields":[{"key":"Model name","value":"Core i7-7820EQ","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-7820EQ","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8067702998607","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR34S","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-7800","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","alternatives":[{"value":"32 GiB","sourceId":"chipswiki-6416-r20015","reason":"Intel/core i7/i7-7820eq · revision 20015 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6416-r20015","location":"Intel/core i7/i7-7820eq · revision 20015 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820eq&oldid=20015","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-1942c7146ed1b70d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6416-r20015","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-1942c7146ed1b70d"},{"id":"cw-1992c67f91d0f419","name":"Atom Z510PT","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z500","year":2009,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z510pt"],"fields":[{"key":"Model name","value":"Atom Z510PT","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z510PT","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CH80566EC005DT","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLGPR","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 2, 2009","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 2, 2009","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z500","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"400 MT/s","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Menlow","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Poulsbo","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Silverthorne","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":28,"unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47212207,"unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":24.18,"unit":"mm²","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2,"unit":"W","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":"-40 °C","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":110,"unit":"°C","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8068-r25704","location":"Intel/atom/z510pt · revision 25704 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz510pt&oldid=25704","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-437","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":437,"unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.6,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1992c67f91d0f419","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8068-r25704","chipswiki-31502-r92564"],"url":"https://museum.vlsi.kr/objects/cw-1992c67f91d0f419"},{"id":"cw-1a1aa932ef061a63","name":"z14","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2017,"process":"14 nm","aliases":["Ibm microarchitectures z14"],"fields":[{"key":"Architecture name","value":"z14","unit":"","sourceId":"chipswiki-1826-r6149","location":"Ibm/microarchitectures/z14 · revision 6149 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. 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Not an independent measurement.","entityId":"cw-1a1aa932ef061a63","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz14&oldid=6149","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":7,"unit":"","sourceId":"chipswiki-1826-r6149","location":"Ibm/microarchitectures/z14 · revision 6149 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. 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Not an independent measurement.","entityId":"cw-1a1aa932ef061a63","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz14&oldid=6149","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"z13","unit":"","sourceId":"chipswiki-1826-r6149","location":"Ibm/microarchitectures/z14 · revision 6149 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-1a1aa932ef061a63","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz14&oldid=6149","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"z15","unit":"","sourceId":"chipswiki-1826-r6149","location":"Ibm/microarchitectures/z14 · revision 6149 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-1a1aa932ef061a63","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz14&oldid=6149","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1826-r6149"],"url":"https://museum.vlsi.kr/objects/cw-1a1aa932ef061a63"},{"id":"cw-1a528d2a8375888e","name":"GAP8","kind":"sku","entityType":"product-model","subtype":"cpu","company":"GreenWaves","year":2018,"process":"55 nm","aliases":["Greenwaves gap8"],"fields":[{"key":"Model name","value":"GAP8","unit":"","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"GreenWaves","unit":"","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"GAP8","unit":"","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October, 2016","unit":"","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 26, 2018","unit":"","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":250,"unit":"MHz","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"RV32IMC","unit":"","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":55,"unit":"nm","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":9,"unit":"","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":9,"unit":"","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":100,"unit":"KiB","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":20,"unit":"KiB","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16 KiB + 4 KiB","unit":"","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":80,"unit":"KiB","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"64 KiB + 16 KiB","unit":"","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x128 KiB","unit":"","sourceId":"chipswiki-7034-r22146","location":"Greenwaves/gap8 · revision 22146 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Greenwaves%2Fgap8&oldid=22146","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"aQFN-84","unit":"","sourceId":"chipswiki-31299-r91993","location":"Template:Packages/greenwaves/aqfn-84 · revision 91993 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fgreenwaves%2Faqfn-84&oldid=91993","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"aQFN","unit":"","sourceId":"chipswiki-31299-r91993","location":"Template:Packages/greenwaves/aqfn-84 · revision 91993 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fgreenwaves%2Faqfn-84&oldid=91993","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":84,"unit":"","sourceId":"chipswiki-31299-r91993","location":"Template:Packages/greenwaves/aqfn-84 · revision 91993 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-28. Not an independent measurement.","entityId":"cw-1a528d2a8375888e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fgreenwaves%2Faqfn-84&oldid=91993","sourceDate":"2018-02-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7034-r22146","chipswiki-31299-r91993"],"url":"https://museum.vlsi.kr/objects/cw-1a528d2a8375888e"},{"id":"cw-1a553cbd3e35103d","name":"Merced","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2001,"process":"180 nm","aliases":["Intel microarchitectures merced"],"fields":[{"key":"Architecture name","value":"Merced","unit":"","sourceId":"chipswiki-837-r2186","location":"Intel/microarchitectures/merced · revision 2186 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-1a553cbd3e35103d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmerced&oldid=2186","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-837-r2186","location":"Intel/microarchitectures/merced · revision 2186 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-1a553cbd3e35103d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmerced&oldid=2186","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-837-r2186","location":"Intel/microarchitectures/merced · revision 2186 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-1a553cbd3e35103d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmerced&oldid=2186","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"June, 2001","unit":"","sourceId":"chipswiki-837-r2186","location":"Intel/microarchitectures/merced · revision 2186 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-1a553cbd3e35103d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmerced&oldid=2186","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-837-r2186","location":"Intel/microarchitectures/merced · revision 2186 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-1a553cbd3e35103d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmerced&oldid=2186","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-837-r2186","location":"Intel/microarchitectures/merced · revision 2186 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-1a553cbd3e35103d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmerced&oldid=2186","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"IA-64","unit":"","sourceId":"chipswiki-837-r2186","location":"Intel/microarchitectures/merced · revision 2186 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-1a553cbd3e35103d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmerced&oldid=2186","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"McKinley","unit":"","sourceId":"chipswiki-837-r2186","location":"Intel/microarchitectures/merced · revision 2186 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-21. Not an independent measurement.","entityId":"cw-1a553cbd3e35103d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmerced&oldid=2186","sourceDate":"2021-01-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-837-r2186"],"url":"https://museum.vlsi.kr/objects/cw-1a553cbd3e35103d"},{"id":"cw-1a5d736306cc2a4f","name":"Xeon E5-2696 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2696 v4"],"fields":[{"key":"Model name","value":"Xeon E5-2696 v4","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2696 v4","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002402501","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2J0","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7200000000,"unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":456.12,"unit":"mm²","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":22,"unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":44,"unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":704,"unit":"KiB","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":704,"unit":"KiB","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":5.5,"unit":"MiB","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"22x256 KiB","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":55,"unit":"MiB","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"22x2.5 MiB","unit":"","sourceId":"chipswiki-7721-r25095","location":"Intel/xeon e5/e5-2696 v4 · revision 25095 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1a5d736306cc2a4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2696%20v4&oldid=25095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7721-r25095"],"url":"https://museum.vlsi.kr/objects/cw-1a5d736306cc2a4f"},{"id":"cw-1a7fd9af1cbca18e","name":"K6-2/550AGR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":2000,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-550agr"],"fields":[{"key":"Model name","value":"K6-2/550AGR","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/550AGR","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/550AGR","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2000","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 22, 2000","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":549.99,"unit":"MHz","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.3,"unit":"V","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8332-r26027","location":"Amd/k6-2/k6-2-550agr · revision 26027 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1a7fd9af1cbca18e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-550agr&oldid=26027","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8332-r26027"],"url":"https://museum.vlsi.kr/objects/cw-1a7fd9af1cbca18e"},{"id":"cw-1a82c454acbb7265","name":"Poulson","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2012,"process":"32 nm","aliases":["Intel microarchitectures poulson"],"fields":[{"key":"Architecture name","value":"Poulson","unit":"","sourceId":"chipswiki-8765-r27227","location":"Intel/microarchitectures/poulson · revision 27227 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-1a82c454acbb7265","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpoulson&oldid=27227","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8765-r27227","location":"Intel/microarchitectures/poulson · revision 27227 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-1a82c454acbb7265","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpoulson&oldid=27227","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8765-r27227","location":"Intel/microarchitectures/poulson · revision 27227 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-1a82c454acbb7265","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpoulson&oldid=27227","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"November 8, 2012","unit":"","sourceId":"chipswiki-8765-r27227","location":"Intel/microarchitectures/poulson · revision 27227 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-1a82c454acbb7265","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpoulson&oldid=27227","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8765-r27227","location":"Intel/microarchitectures/poulson · revision 27227 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-1a82c454acbb7265","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpoulson&oldid=27227","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-8765-r27227","location":"Intel/microarchitectures/poulson · revision 27227 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-1a82c454acbb7265","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpoulson&oldid=27227","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"IA-64","unit":"","sourceId":"chipswiki-8765-r27227","location":"Intel/microarchitectures/poulson · revision 27227 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-1a82c454acbb7265","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpoulson&oldid=27227","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Tukwila","unit":"","sourceId":"chipswiki-8765-r27227","location":"Intel/microarchitectures/poulson · revision 27227 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-1a82c454acbb7265","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpoulson&oldid=27227","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Kittson","unit":"","sourceId":"chipswiki-8765-r27227","location":"Intel/microarchitectures/poulson · revision 27227 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-1a82c454acbb7265","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpoulson&oldid=27227","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8765-r27227"],"url":"https://museum.vlsi.kr/objects/cw-1a82c454acbb7265"},{"id":"cw-1aa3a22c6dd7df03","name":"Ryzen 7 2700E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000","year":2018,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 7 2700e"],"fields":[{"key":"Model name","value":"Ryzen 7 2700E","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2700E","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD270EBHM88AF","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 10, 2018","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 10, 2018","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2000,"unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Pinnacle Ridge","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x64 KiB","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x8 MiB","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-4896-r15760","location":"Amd/ryzen 7/2700e · revision 15760 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2700e&oldid=15760","sourceDate":"2018-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-10. Not an independent measurement.","entityId":"cw-1aa3a22c6dd7df03","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4896-r15760","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-1aa3a22c6dd7df03"},{"id":"cw-1ab63bdb1a414de6","name":"AM9080A-2PCB","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080a-2pcb"],"fields":[{"key":"Model name","value":"AMD AM9080A-2PCB","unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080A-2PCB","unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080A-2PCB","unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.632,"unit":"MHz","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"DIP-40","unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"DIP","unit":"","sourceId":"chipswiki-8475-r26668","location":"Amd/am9080/am9080a-2pcb · revision 26668 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ab63bdb1a414de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2pcb&oldid=26668","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8475-r26668"],"url":"https://museum.vlsi.kr/objects/cw-1ab63bdb1a414de6"},{"id":"cw-1ae284875404390a","name":"CN3010-500 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3000","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3010-500bg525-scp"],"fields":[{"key":"Model name","value":"Cavium CN3010-500 SCP","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3010-500 SCP","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3010-500BG525-SCP","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3000","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":24,"unit":"KiB","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":1.986,"unit":"GiB/s","sourceId":"chipswiki-8270-r25930","location":"Cavium/octeon/cn3010-500bg525-scp · revision 25930 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae284875404390a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-500bg525-scp&oldid=25930","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8270-r25930"],"url":"https://museum.vlsi.kr/objects/cw-1ae284875404390a"},{"id":"cw-1ae7c905c88b4212","name":"J80186-1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1984,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 j80186-1"],"fields":[{"key":"Model name","value":"J80186-1","unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J80186-1","unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"J80186-1","unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"J80186-1B","unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":10,"unit":"MHz","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"2.5 MT/s","unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-68","unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PLCC-68","unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8639-r26838","location":"Amd/am186/j80186-1 · revision 26838 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ae7c905c88b4212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fj80186-1&oldid=26838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8639-r26838"],"url":"https://museum.vlsi.kr/objects/cw-1ae7c905c88b4212"},{"id":"cw-1af7a7551ea318e8","name":"Core i5-2435M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2435m"],"fields":[{"key":"Model name","value":"Core i5-2435M","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2435M","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700995706","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR06Y","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October, 2011","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October, 2011","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-7960-r25510","location":"Intel/core i5/i5-2435m · revision 25510 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2435m&oldid=25510","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1af7a7551ea318e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7960-r25510","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-1af7a7551ea318e8"},{"id":"cw-1afdd35797e0f9cf","name":"EPYC 7251","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7000","year":2017,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc 7251"],"fields":[{"key":"Model name","value":"EPYC 7251","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7251,"unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PS7251BFV8SAF","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PS7251BFAFWOF","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7000,"unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Naples","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":19200000000,"unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":120,"unit":"W","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x64 KiB","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x8 MiB","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":143.1,"unit":"GiB/s","sourceId":"chipswiki-3831-r12102","location":"Amd/epyc/7251 · revision 12102 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7251&oldid=12102","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-4094","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket SP3","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-1afdd35797e0f9cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3831-r12102","chipswiki-31468-r92417"],"url":"https://museum.vlsi.kr/objects/cw-1afdd35797e0f9cf"},{"id":"cw-1b473fea315c9458","name":"CN5830-800 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5830-800bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN5830-800 NSP","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5830-800 NSP","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5830-800BG1521-NSP","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x16 KiB","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-nsp&oldid=25813","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8154-r25813","location":"Cavium/octeon plus/cn5830-800bg1521-nsp · revision 25813 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1b473fea315c9458","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2355M","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701312800","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0U2","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2012,"unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8007-r25588","location":"Intel/core i3/i3-2355m · revision 25588 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2355m&oldid=25588","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1b8083404cca0c8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SDM730G","unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 9, 2019","unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 9, 2019","unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 700","unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2200,"unit":"MHz","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1800,"unit":"MHz","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2021-09-26. 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Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A76","unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 470 Gold","unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 470 Silver","unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":8,"unit":"nm","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. 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Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. Not an independent measurement.","entityId":"cw-1b99bc0e9066c8a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730g&oldid=1395","sourceDate":"2021-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 618","unit":"","sourceId":"chipswiki-598-r1395","location":"Qualcomm/snapdragon 700/730g · revision 1395 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-26. 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Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 1994","unit":"","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX4","unit":"","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":90,"unit":"MHz","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"30 MT/s","unit":"","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX4","unit":"","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8547-r26743","location":"Amd/am486/am486dx4-90 · revision 26743 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1baff1652f4b9b61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-90&oldid=26743","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8547-r26743"],"url":"https://museum.vlsi.kr/objects/cw-1baff1652f4b9b61"},{"id":"cw-1bc872098d25218e","name":"Akida","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"BrainChip","year":2018,"process":"28nm or 14nm","aliases":["Brainchip akida"],"fields":[{"key":"Architecture name","value":"Akida","unit":"","sourceId":"chipswiki-4738-r15252","location":"Brainchip/akida · revision 15252 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-28. Not an independent measurement.","entityId":"cw-1bc872098d25218e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Brainchip%2Fakida&oldid=15252","sourceDate":"2018-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"BrainChip","unit":"","sourceId":"chipswiki-4738-r15252","location":"Brainchip/akida · revision 15252 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-28. Not an independent measurement.","entityId":"cw-1bc872098d25218e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Brainchip%2Fakida&oldid=15252","sourceDate":"2018-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4738-r15252","location":"Brainchip/akida · revision 15252 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-28. Not an independent measurement.","entityId":"cw-1bc872098d25218e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Brainchip%2Fakida&oldid=15252","sourceDate":"2018-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"September 10, 2018","unit":"","sourceId":"chipswiki-4738-r15252","location":"Brainchip/akida · revision 15252 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-28. Not an independent measurement.","entityId":"cw-1bc872098d25218e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Brainchip%2Fakida&oldid=15252","sourceDate":"2018-09-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"28nm or 14nm","unit":"","sourceId":"chipswiki-4738-r15252","location":"Brainchip/akida · revision 15252 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-28. Not an independent measurement.","entityId":"cw-1bc872098d25218e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Brainchip%2Fakida&oldid=15252","sourceDate":"2018-09-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4738-r15252"],"url":"https://museum.vlsi.kr/objects/cw-1bc872098d25218e"},{"id":"cw-1c0c72fa1ec5016b","name":"Xeon Gold 6258R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2020,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6258r"],"fields":[{"key":"Model name","value":"Xeon Gold 6258R","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6258R","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake R","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1267-r4102","location":"Intel/xeon gold/6258r · revision 4102 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1c0c72fa1ec5016b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6258r&oldid=4102","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1267-r4102"],"url":"https://museum.vlsi.kr/objects/cw-1c0c72fa1ec5016b"},{"id":"cw-1c57a965737d919a","name":"CN5830-1000 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5830-1000bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN5830-1000 EXP","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5830-1000 EXP","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5830-1000BG1521-EXP","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x16 KiB","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8161-r25820","location":"Cavium/octeon plus/cn5830-1000bg1521-exp · revision 25820 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-1000bg1521-exp&oldid=25820","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c57a965737d919a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8161-r25820","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-1c57a965737d919a"},{"id":"cw-1c5e4553a4fe586c","name":"Xeon E-2186M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2186m"],"fields":[{"key":"Model name","value":"Xeon E-2186M","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2186M","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8068403359021","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRCKQ","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2000","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4600,"unit":"MHz","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake H","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-2400-r8023","location":"Intel/xeon e/e-2186m · revision 8023 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186m&oldid=8023","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-1c5e4553a4fe586c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2400-r8023","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-1c5e4553a4fe586c"},{"id":"cw-1c7902047a7054d2","name":"IR80186","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1985,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 ir80186"],"fields":[{"key":"Model name","value":"IR80186","unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"IR80186","unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"IR80186B","unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1985,"unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"2 MT/s","unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CLCC-68","unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CLCC","unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CLCC-68","unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8640-r26839","location":"Amd/am186/ir80186 · revision 26839 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1c7902047a7054d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fir80186&oldid=26839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8640-r26839"],"url":"https://museum.vlsi.kr/objects/cw-1c7902047a7054d2"},{"id":"cw-1ca5f5ccc5748c16","name":"CN3120-500 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3120-500bg868-scp"],"fields":[{"key":"Model name","value":"Cavium CN3120-500 SCP","unit":"","sourceId":"chipswiki-8242-r25902","location":"Cavium/octeon/cn3120-500bg868-scp · revision 25902 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ca5f5ccc5748c16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-scp&oldid=25902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8242-r25902","location":"Cavium/octeon/cn3120-500bg868-scp · revision 25902 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1ca5f5ccc5748c16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-scp&oldid=25902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8242-r25902","location":"Cavium/octeon/cn3120-500bg868-scp · revision 25902 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1ca5f5ccc5748c16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-scp&oldid=25902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8242-r25902","location":"Cavium/octeon/cn3120-500bg868-scp · revision 25902 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1ca5f5ccc5748c16","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-scp&oldid=25902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8242-r25902","location":"Cavium/octeon/cn3120-500bg868-scp · revision 25902 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1ca5f5ccc5748c16","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-scp&oldid=25902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8242-r25902","location":"Cavium/octeon/cn3120-500bg868-scp · revision 25902 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ca5f5ccc5748c16","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-scp&oldid=25902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8242-r25902","location":"Cavium/octeon/cn3120-500bg868-scp · revision 25902 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ca5f5ccc5748c16","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-scp&oldid=25902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8242-r25902","location":"Cavium/octeon/cn3120-500bg868-scp · revision 25902 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ca5f5ccc5748c16","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-scp&oldid=25902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8242-r25902","location":"Cavium/octeon/cn3120-500bg868-scp · revision 25902 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ca5f5ccc5748c16","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-scp&oldid=25902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8242-r25902","location":"Cavium/octeon/cn3120-500bg868-scp · revision 25902 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ca5f5ccc5748c16","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-scp&oldid=25902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8242-r25902","location":"Cavium/octeon/cn3120-500bg868-scp · revision 25902 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ca5f5ccc5748c16","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-scp&oldid=25902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ca5f5ccc5748c16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ca5f5ccc5748c16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ca5f5ccc5748c16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8242-r25902","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-1ca5f5ccc5748c16"},{"id":"cw-1cd3858d0b4da877","name":"Core i3-8000","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-8000"],"fields":[{"key":"Model name","value":"Core i3-8000","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8000","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3XL","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March, 2018","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2018","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-8000","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. 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Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. Not an independent measurement.","entityId":"cw-1cd3858d0b4da877","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8000&oldid=17749","sourceDate":"2018-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-5451-r17749","location":"Intel/core i3/i3-8000 · revision 17749 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-03. 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Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2NT","unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1168","unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1168","unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cd46558a3daf27e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7862-r25363","location":"Intel/core i7/i7-5500du · revision 25363 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 2000+","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMSN2000DUT3C","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 27, 2002","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 27, 2002","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1667,"unit":"MHz","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Thoroughbred","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37200000,"unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":85,"unit":"mm²","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":58.2,"unit":"W","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8451-r26644","location":"Amd/athlon mp/amsn2000dut3c · revision 26644 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dut3c&oldid=26644","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OPGA-453","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"OPGA","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":453,"unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.942,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1cdc4e19449a471c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2637 v4","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002041100","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2P3","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":135,"unit":"W","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":10,"unit":"MiB","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2.5 MiB","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7739-r25116","location":"Intel/xeon e5/e5-2637 v4 · revision 25116 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d014819dd02b060","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2637%20v4&oldid=25116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7739-r25116"],"url":"https://museum.vlsi.kr/objects/cw-1d014819dd02b060"},{"id":"cw-1d14230599bdf4d2","name":"Core i5-7300U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-7300","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i5 i5-7300u"],"fields":[{"key":"Model name","value":"Core i5-7300U","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-7300U","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR340","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-7300","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. 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Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. 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Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 620","unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. 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Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. 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Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-317-r634","location":"Intel/core i5/i5-7300u · revision 634 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7300u&oldid=634","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. 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Not an independent measurement.","entityId":"cw-1d14230599bdf4d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. 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Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake R","unit":"","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":20,"unit":"MiB","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x1 MiB","unit":"","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-1d278e29119ce09f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218r&oldid=4091","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":27.5,"unit":"MiB","sourceId":"chipswiki-1260-r4091","location":"Intel/xeon gold/5218r · revision 4091 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":4210,"unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069503956302","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806954210","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2020-01-24. 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Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4200,"unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. 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Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R1","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. 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Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":10,"unit":"MiB","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x1","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":13.75,"unit":"MiB","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. 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Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. 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Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1374-r4596","location":"Intel/xeon silver/4210 · revision 4596 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-24. Not an independent measurement.","entityId":"cw-1d58772ea9f5abad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210&oldid=4596","sourceDate":"2020-01-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1374-r4596"],"url":"https://museum.vlsi.kr/objects/cw-1d58772ea9f5abad"},{"id":"cw-1d832b27937974f4","name":"Core i7-840QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":2010,"architecture":"Nehalem","process":"45 nm","aliases":["Intel core i7 i7-840qm"],"fields":[{"key":"Model name","value":"Intel Core i7-840QM","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-840QM","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BY80607002901AI","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80607I7840QM","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 22, 2010","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 22, 2010","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1866.66,"unit":"MHz","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3199.99,"unit":"MHz","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBMP","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Nehalem","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Clarksfield","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":30,"unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":774000000,"unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":296,"unit":"mm²","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.075,"unit":"V","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988A","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"rPGA","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket G1","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"no","unit":"","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7828-r25301","location":"Intel/core i7/i7-840qm · revision 25301 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1d832b27937974f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-840qm&oldid=25301","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7828-r25301"],"url":"https://museum.vlsi.kr/objects/cw-1d832b27937974f4"},{"id":"cw-1da2671e0dfab09a","name":"Core i7-620UM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-600","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i7 i7-620um"],"fields":[{"key":"Model name","value":"Intel Core i7-620UM","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-620UM","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617003882AE","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-600","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1066.66,"unit":"MHz","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2133.33,"unit":"MHz","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBMN","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBSX","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1da2671e0dfab09a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620um&oldid=25351","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7852-r25351","location":"Intel/core i7/i7-620um · revision 25351 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1dc72b7112b5ef26","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsunny%20cove&oldid=402","sourceDate":"2022-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ice Lake (Client)","unit":"","sourceId":"chipswiki-201-r402","location":"Intel/microarchitectures/sunny cove · revision 402 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2022-09-14. Not an independent measurement.","entityId":"cw-1dc72b7112b5ef26","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsunny%20cove&oldid=402","sourceDate":"2022-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ice Lake (Server)","unit":"","sourceId":"chipswiki-201-r402","location":"Intel/microarchitectures/sunny cove · revision 402 · {{microarchitecture}} / core name 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 4","note":"Source-reported parameter; source revision 2022-09-14. Not an independent measurement.","entityId":"cw-1dc72b7112b5ef26","scope":"core name 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsunny%20cove&oldid=402","sourceDate":"2022-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Palm Cove","unit":"","sourceId":"chipswiki-201-r402","location":"Intel/microarchitectures/sunny cove · revision 402 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-14. Not an independent measurement.","entityId":"cw-1dc72b7112b5ef26","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsunny%20cove&oldid=402","sourceDate":"2022-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Willow Cove","unit":"","sourceId":"chipswiki-201-r402","location":"Intel/microarchitectures/sunny cove · revision 402 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-14. Not an independent measurement.","entityId":"cw-1dc72b7112b5ef26","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsunny%20cove&oldid=402","sourceDate":"2022-09-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-201-r402"],"url":"https://museum.vlsi.kr/objects/cw-1dc72b7112b5ef26"},{"id":"cw-1ddda6064e382cbf","name":"Hi1612","kind":"sku","entityType":"product-model","subtype":"cpu","company":"HiSilicon","year":2016,"architecture":"Cortex-A57","process":"16 nm","aliases":["Hisilicon kunpeng hi1612"],"fields":[{"key":"Model name","value":"Hi1612","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"HiSilicon","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Hi1612","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 4, 2016","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 4, 2016","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Hi16xx","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A57","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A57","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2.5,"unit":"MiB","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. 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Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. 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Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. 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Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32x256 KiB","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. 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Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"32x1 MiB","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":63.58,"unit":"GiB/s","sourceId":"chipswiki-2917-r9737","location":"Hisilicon/kunpeng/hi1612 · revision 9737 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-1ddda6064e382cbf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2Fhi1612&oldid=9737","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2917-r9737"],"url":"https://museum.vlsi.kr/objects/cw-1ddda6064e382cbf"},{"id":"cw-1df11c2fdb86f7d0","name":"Core i5-8550","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":null,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i5 i5-8550"],"fields":[{"key":"Model name","value":"Core i5-8550","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8550","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. 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Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4966-r16062","location":"Intel/core i5/i5-8550 · revision 16062 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-1df11c2fdb86f7d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8550&oldid=16062","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4966-r16062"],"url":"https://museum.vlsi.kr/objects/cw-1df11c2fdb86f7d0"},{"id":"cw-1e14917902e253bc","name":"Core i7-2710QE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2710qe"],"fields":[{"key":"Model name","value":"Core i7-2710QE","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2710QE","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700841002","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR02T","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 2011","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2011","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":216,"unit":"mm²","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":23.84,"unit":"GiB/s","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-7879-r25383","location":"Intel/core i7/i7-2710qe · revision 25383 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e14917902e253bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7879-r25383","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-1e14917902e253bc"},{"id":"cw-1e270fcd1f77e04c","name":"i486SX-20","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486SX","year":1991,"architecture":"80486","process":"1 µm","aliases":["Intel 80486 486sx-20"],"fields":[{"key":"Model name","value":"Intel i486SX-20","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486SX-20","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486SX-20","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KU80486SX-20","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"03G9565","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 16, 1991","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486SX","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"20 MT/s","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX406","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX467","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX492","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX678","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SXE63","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / s-spec 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 5","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"s-spec 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX587","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / s-spec 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 6","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"s-spec 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX632","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / s-spec 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 7","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"s-spec 7","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX672","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / s-spec 8","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 8","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"s-spec 8","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SZ700","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / s-spec 9","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 9","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"s-spec 9","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SZ740","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / s-spec 10","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 10","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"s-spec 10","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SX","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1,"unit":"µm","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1185000,"unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8080-r25731","location":"Intel/80486/486sx-20 · revision 25731 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e270fcd1f77e04c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-20&oldid=25731","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8080-r25731"],"url":"https://museum.vlsi.kr/objects/cw-1e270fcd1f77e04c"},{"id":"cw-1e2a30da5de09c34","name":"Ryzen 5 4600H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 5 4600h"],"fields":[{"key":"Model name","value":"Ryzen 5 4600H","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4600H","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000100","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. 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Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. 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Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-1e2a30da5de09c34","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600h&oldid=1677","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-683-r1677","location":"Amd/ryzen 5/4600h · revision 1677 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. 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Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-6000","unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":900,"unit":"MHz","sourceId":"chipswiki-3969-r12656","location":"Intel/core i3/i3-6100h · revision 12656 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6100h&oldid=12656","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-1e386e550ebbd74c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3969-r12656","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-1e386e550ebbd74c"},{"id":"cw-1e3dad5d3f74463e","name":"MD8086-2","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"M8086","year":null,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 md8086-2"],"fields":[{"key":"Model name","value":"AMD MD8086-2","unit":"","sourceId":"chipswiki-8501-r26694","location":"Amd/am8086/md8086-2 · revision 26694 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1e3dad5d3f74463e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2&oldid=26694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8501-r26694","location":"Amd/am8086/md8086-2 · revision 26694 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e3dad5d3f74463e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2&oldid=26694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MD8086-2","unit":"","sourceId":"chipswiki-8501-r26694","location":"Amd/am8086/md8086-2 · revision 26694 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e3dad5d3f74463e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2&oldid=26694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MD8086-2","unit":"","sourceId":"chipswiki-8501-r26694","location":"Amd/am8086/md8086-2 · revision 26694 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e3dad5d3f74463e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2&oldid=26694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Military","unit":"","sourceId":"chipswiki-8501-r26694","location":"Amd/am8086/md8086-2 · revision 26694 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e3dad5d3f74463e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2&oldid=26694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8501-r26694","location":"Amd/am8086/md8086-2 · revision 26694 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e3dad5d3f74463e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2&oldid=26694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"M8086","unit":"","sourceId":"chipswiki-8501-r26694","location":"Amd/am8086/md8086-2 · revision 26694 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e3dad5d3f74463e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2&oldid=26694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8501-r26694","location":"Amd/am8086/md8086-2 · revision 26694 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e3dad5d3f74463e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2&oldid=26694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8501-r26694","location":"Amd/am8086/md8086-2 · revision 26694 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1e3dad5d3f74463e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2&oldid=26694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8501-r26694","location":"Amd/am8086/md8086-2 · revision 26694 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e3dad5d3f74463e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086-2&oldid=26694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8501-r26694","location":"Amd/am8086/md8086-2 · revision 26694 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6230T","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":640,"unit":"KiB","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":20,"unit":"MiB","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x1 MiB","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":27.5,"unit":"MiB","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"20x1.375 MiB","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1489-r4940","location":"Intel/xeon gold/6230t · revision 4940 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-1e73c8d6db3ef665","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230t&oldid=4940","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1489-r4940"],"url":"https://museum.vlsi.kr/objects/cw-1e73c8d6db3ef665"},{"id":"cw-1e878220fcaa9897","name":"CN3860-400 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3860-400bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN3860-400 SCP","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3860-400 SCP","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3860-400BG1521-SCP","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x8 KiB","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8200-r25859","location":"Cavium/octeon/cn3860-400bg1521-scp · revision 25859 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-scp&oldid=25859","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1e878220fcaa9897","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8200-r25859","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-1e878220fcaa9897"},{"id":"cw-1ebebfef06bc8086","name":"Core M 5Y71","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel core m 5y71"],"fields":[{"key":"Model name","value":"Core M 5Y71","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5Y71","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8065802061602","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2014","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2015","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core M","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR23Q","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell Y","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"3D","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"F0","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1300000000,"unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":82,"unit":"mm²","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1234","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-1ebebfef06bc8086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y71&oldid=2620","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-937-r2620","location":"Intel/core m/5y71 · revision 2620 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. 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Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1548","unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067402569300","unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2DJ","unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 1, 2015","unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.5 MiB","unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-763-r1861","location":"Intel/xeon d/d-1548 · revision 1861 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-1ec98ee12d3eb013","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1548&oldid=1861","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-763-r1861"],"url":"https://museum.vlsi.kr/objects/cw-1ec98ee12d3eb013"},{"id":"cw-1f078d4a36a13079","name":"Core i7-2667M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2667m"],"fields":[{"key":"Model name","value":"Core i7-2667M","unit":"","sourceId":"chipswiki-7886-r25390","location":"Intel/core i7/i7-2667m · revision 25390 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f078d4a36a13079","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2667m&oldid=25390","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7886-r25390","location":"Intel/core i7/i7-2667m · revision 25390 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f078d4a36a13079","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2667m&oldid=25390","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7886-r25390","location":"Intel/core i7/i7-2667m · revision 25390 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f078d4a36a13079","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2667m&oldid=25390","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2667M","unit":"","sourceId":"chipswiki-7886-r25390","location":"Intel/core i7/i7-2667m · revision 25390 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1f078d4a36a13079","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2667m&oldid=25390","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7886-r25390","location":"Intel/core i7/i7-2667m · revision 25390 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f078d4a36a13079","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2667m&oldid=25390","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7886-r25390","location":"Intel/core i7/i7-2667m · revision 25390 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f078d4a36a13079","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2667m&oldid=25390","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7886-r25390","location":"Intel/core i7/i7-2667m · revision 25390 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f078d4a36a13079","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2667m&oldid=25390","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7886-r25390","location":"Intel/core i7/i7-2667m · revision 25390 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1f078d4a36a13079","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2667m&oldid=25390","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7886-r25390","location":"Intel/core i7/i7-2667m · revision 25390 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1f078d4a36a13079","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2667m&oldid=25390","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7886-r25390","location":"Intel/core i7/i7-2667m · revision 25390 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f078d4a36a13079","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2667m&oldid=25390","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7886-r25390","location":"Intel/core i7/i7-2667m · revision 25390 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1f078d4a36a13079","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2667m&oldid=25390","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7886-r25390","location":"Intel/core i7/i7-2667m · revision 25390 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1f078d4a36a13079","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2667m&oldid=25390","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7886-r25390","location":"Intel/core i7/i7-2667m · revision 25390 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1f1b33fb8a25c0f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310e&oldid=25599","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8018-r25599","location":"Intel/core i3/i3-2310e · revision 25599 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1f1b33fb8a25c0f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2310e&oldid=25599","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8018-r25599","location":"Intel/core i3/i3-2310e · revision 25599 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2600,"unit":"MHz","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-7899-r25403","location":"Intel/core i7/i7-2617m · revision 25403 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f26b492e77036ee","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7899-r25403","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-1f26b492e77036ee"},{"id":"cw-1f4e8ebec1ac628b","name":"Xeon Gold 6161","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":null,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6161"],"fields":[{"key":"Model name","value":"Xeon Gold 6161","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6161,"unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. 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Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":22,"unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":44,"unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.375,"unit":"MiB","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":704,"unit":"KiB","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":704,"unit":"KiB","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":22,"unit":"MiB","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"22x1 MiB","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":30.25,"unit":"MiB","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"22x1.375 MiB","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-2472-r8398","location":"Intel/xeon gold/6161 · revision 8398 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-1f4e8ebec1ac628b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6161&oldid=8398","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2472-r8398"],"url":"https://museum.vlsi.kr/objects/cw-1f4e8ebec1ac628b"},{"id":"cw-1f5c0b91597519f9","name":"Xeon D-1527","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1527"],"fields":[{"key":"Model name","value":"Xeon D-1527","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1527","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067402569400","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2DK","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 1, 2015","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 1, 2015","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2700,"unit":"MHz","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"V2","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-1f5c0b91597519f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1527&oldid=11448","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3739-r11448","location":"Intel/xeon d/d-1527 · revision 11448 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-8010-r25591","location":"Intel/core i3/i3-2348m · revision 25591 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2348m&oldid=25591","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1f68c5bcde364bfb","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8010-r25591","chipswiki-31339-r92076","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-1f68c5bcde364bfb"},{"id":"cw-1f9dd9e85a2daf0b","name":"K6-2+/450ACZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2+ Mobile","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-2+ k6-2+-450acz"],"fields":[{"key":"Model name","value":"K6-2+/450ACZ","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2+/450ACZ","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2+/450ACZ","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":450,"unit":"MHz","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":16,"unit":"W","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 18, 2000","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2+","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2+ Mobile","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"100 MT/s","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":5,"unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":6,"unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":7,"unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-993-r2839","location":"Amd/k6-2+/k6-2+-450acz · revision 2839 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-450acz&oldid=2839","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":321,"unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":2.54,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":3.3,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super Socket 7","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-1f9dd9e85a2daf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-993-r2839","chipswiki-31126-r91598"],"url":"https://museum.vlsi.kr/objects/cw-1f9dd9e85a2daf0b"},{"id":"cw-1fd77b2a7ec6207b","name":"EPYC 7502","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7502"],"fields":[{"key":"Model name","value":"EPYC 7502","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7502,"unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000054","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000054WOF","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3350,"unit":"MHz","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":180,"unit":"W","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32x512 KiB","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x16 MiB","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-862-r2245","location":"Amd/epyc/7502 · revision 2245 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-1fd77b2a7ec6207b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7502&oldid=2245","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-862-r2245"],"url":"https://museum.vlsi.kr/objects/cw-1fd77b2a7ec6207b"},{"id":"cw-1fefe60b63a9eb97","name":"Pentium G4500T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel pentium (2009) g4500t"],"fields":[{"key":"Model name","value":"Pentium G4500T","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4500T","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201927512","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2HS","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Skylake","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-7785-r25220","location":"Intel/pentium (2009)/g4500t · revision 25220 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1fefe60b63a9eb97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500t&oldid=25220","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7785-r25220"],"url":"https://museum.vlsi.kr/objects/cw-1fefe60b63a9eb97"},{"id":"cw-1ff0ccecefbe1d20","name":"CN5850-900 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5850-900bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN5850-900 NSP","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5850-900 NSP","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5850-900BG1521-NSP","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8127-r25786","location":"Cavium/octeon plus/cn5850-900bg1521-nsp · revision 25786 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-nsp&oldid=25786","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff0ccecefbe1d20","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8127-r25786","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-1ff0ccecefbe1d20"},{"id":"cw-1ff33976d2b666f5","name":"CN5840-600 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5840-600bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN5840-600 NSP","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5840-600 NSP","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5840-600BG1521-NSP","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8145-r25804","location":"Cavium/octeon plus/cn5840-600bg1521-nsp · revision 25804 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-600bg1521-nsp&oldid=25804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-1ff33976d2b666f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-20008e22784579d3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Fmicroarchitectures%2Fnvdla&oldid=433","sourceDate":"2022-09-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-213-r433","location":"Nvidia/microarchitectures/nvdla · revision 433 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-01. 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Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4109T","unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303562200","unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3GP","unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":11,"unit":"MiB","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.375 MiB","unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1452-r4896","location":"Intel/xeon silver/4109t · revision 4896 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20130a6b5aef2562","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4109t&oldid=4896","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1452-r4896"],"url":"https://museum.vlsi.kr/objects/cw-20130a6b5aef2562"},{"id":"cw-2019f12468196dd9","name":"R-Car M1S","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Renesas","series":"1st Gen","year":2012,"architecture":"SH-4A","process":"40 nm","aliases":["Renesas r-car m1s"],"fields":[{"key":"Model name","value":"R-Car M1S","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Renesas","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"M1S","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"R8A77780","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 16, 2011","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2012","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"R-Car","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"1st Gen","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"SuperH","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"SH-4A","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"SH-4A","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"GiB","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":3.97,"unit":"GiB/s","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX540","unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":200,"unit":"MHz","sourceId":"chipswiki-7646-r24906","location":"Renesas/r-car/m1s · revision 24906 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm1s&oldid=24906","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-472","unit":"","sourceId":"chipswiki-31427-r92297","location":"Template:Packages/renesas/fcbga-472 · revision 92297 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-472&oldid=92297","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31427-r92297","location":"Template:Packages/renesas/fcbga-472 · revision 92297 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-472&oldid=92297","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31427-r92297","location":"Template:Packages/renesas/fcbga-472 · revision 92297 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-472&oldid=92297","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":21,"unit":"mm","sourceId":"chipswiki-31427-r92297","location":"Template:Packages/renesas/fcbga-472 · revision 92297 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-472&oldid=92297","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":21,"unit":"mm","sourceId":"chipswiki-31427-r92297","location":"Template:Packages/renesas/fcbga-472 · revision 92297 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2019f12468196dd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-472&oldid=92297","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7646-r24906","chipswiki-31427-r92297"],"url":"https://museum.vlsi.kr/objects/cw-2019f12468196dd9"},{"id":"cw-207a0eb93e9e21d0","name":"Core i5-8350U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i5 i5-8350u"],"fields":[{"key":"Model name","value":"Core i5-8350U","unit":"","sourceId":"chipswiki-4366-r14118","location":"Intel/core i5/i5-8350u · revision 14118 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-207a0eb93e9e21d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8350u&oldid=14118","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4366-r14118","location":"Intel/core i5/i5-8350u · revision 14118 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. 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Not an independent measurement.","entityId":"cw-207a0eb93e9e21d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8350u&oldid=14118","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8350U","unit":"","sourceId":"chipswiki-4366-r14118","location":"Intel/core i5/i5-8350u · revision 14118 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-207a0eb93e9e21d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8350u&oldid=14118","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8067703282016","unit":"","sourceId":"chipswiki-4366-r14118","location":"Intel/core i5/i5-8350u · revision 14118 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. 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Not an independent measurement.","entityId":"cw-207a0eb93e9e21d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8350u&oldid=14118","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4366-r14118","location":"Intel/core i5/i5-8350u · revision 14118 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. 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Not an independent measurement.","entityId":"cw-207a0eb93e9e21d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8350u&oldid=14118","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-4366-r14118","location":"Intel/core i5/i5-8350u · revision 14118 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. 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Not an independent measurement.","entityId":"cw-207a0eb93e9e21d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8350u&oldid=14118","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-4366-r14118","location":"Intel/core i5/i5-8350u · revision 14118 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-11-23. 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Not an independent measurement.","entityId":"cw-207a0eb93e9e21d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8350u&oldid=14118","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4366-r14118","location":"Intel/core i5/i5-8350u · revision 14118 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-207a0eb93e9e21d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8350u&oldid=14118","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":123,"unit":"mm²","sourceId":"chipswiki-4366-r14118","location":"Intel/core i5/i5-8350u · revision 14118 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. 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Not an independent measurement.","entityId":"cw-207a0eb93e9e21d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8350u&oldid=14118","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-4366-r14118","location":"Intel/core i5/i5-8350u · revision 14118 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. 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Not an independent measurement.","entityId":"cw-207a0eb93e9e21d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8350u&oldid=14118","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-4366-r14118","location":"Intel/core i5/i5-8350u · revision 14118 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. Not an independent measurement.","entityId":"cw-207a0eb93e9e21d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8350u&oldid=14118","sourceDate":"2018-11-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-4366-r14118","location":"Intel/core i5/i5-8350u · revision 14118 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-23. 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Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5860-800 NSP","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5860-800BG1521-NSP","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x16 KiB","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8118-r25777","location":"Cavium/octeon plus/cn5860-800bg1521-nsp · revision 25777 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-nsp&oldid=25777","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-20849679fb564c50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8118-r25777","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-20849679fb564c50"},{"id":"cw-20bbbeb65c96f087","name":"Xeon Gold 6138T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6138t"],"fields":[{"key":"Model name","value":"Xeon Gold 6138T","unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6138T","unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303592900","unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3J7","unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-20bbbeb65c96f087","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138t&oldid=4957","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":27.5,"unit":"MiB","sourceId":"chipswiki-1505-r4957","location":"Intel/xeon gold/6138t · revision 4957 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 900","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHD900AMT1B","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2001","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2001","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25180000,"unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":105.68,"unit":"mm²","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.75,"unit":"V","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":42.7,"unit":"W","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8421-r26129","location":"Amd/duron/dhd900amt1b · revision 26129 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2104c9e4c12e302d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd900amt1b&oldid=26129","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8421-r26129"],"url":"https://museum.vlsi.kr/objects/cw-2104c9e4c12e302d"},{"id":"cw-210aef106f920962","name":"Xeon Platinum 9242","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"9200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 9242"],"fields":[{"key":"Model name","value":"Xeon Platinum 9242","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":9242,"unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":9200,"unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Walker Pass","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake AP","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":48,"unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":96,"unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":350,"unit":"W","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":3,"unit":"MiB","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"48x32 KiB","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"48x32 KiB","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":48,"unit":"MiB","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"48x1 MiB","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":71.5,"unit":"MiB","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"52x1.375 MiB","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":12,"unit":"","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":262.26,"unit":"GiB/s","sourceId":"chipswiki-3702-r11249","location":"Intel/xeon platinum/9242 · revision 11249 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-210aef106f920962","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9242&oldid=11249","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3702-r11249"],"url":"https://museum.vlsi.kr/objects/cw-210aef106f920962"},{"id":"cw-216d0319ddde4851","name":"Core i3-380UM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-300","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i3 i3-380um"],"fields":[{"key":"Model name","value":"Intel Core i3-380UM","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-380UM","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617005190AF","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 1, 2010","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1, 2010","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-300","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1333.33,"unit":"MHz","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBSL","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":166,"unit":"MHz","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":500,"unit":"MHz","sourceId":"chipswiki-7990-r25569","location":"Intel/core i3/i3-380um · revision 25569 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380um&oldid=25569","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-216d0319ddde4851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2172bc4a2109704e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120t&oldid=4978","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1526-r4978","location":"Intel/xeon gold/5120t · revision 4978 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2172bc4a2109704e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120t&oldid=4978","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1526-r4978","location":"Intel/xeon gold/5120t · revision 4978 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-2172bc4a2109704e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120t&oldid=4978","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1526-r4978","location":"Intel/xeon gold/5120t · revision 4978 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2172bc4a2109704e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120t&oldid=4978","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-1526-r4978","location":"Intel/xeon gold/5120t · revision 4978 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-2172bc4a2109704e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120t&oldid=4978","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1526-r4978","location":"Intel/xeon gold/5120t · revision 4978 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-2172bc4a2109704e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120t&oldid=4978","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":14,"unit":"","sourceId":"chipswiki-1526-r4978","location":"Intel/xeon gold/5120t · revision 4978 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-2172bc4a2109704e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120t&oldid=4978","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-1526-r4978","location":"Intel/xeon gold/5120t · revision 4978 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-2172bc4a2109704e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5120t&oldid=4978","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x1 MiB","unit":"","sourceId":"chipswiki-1526-r4978","location":"Intel/xeon gold/5120t · revision 4978 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-6413-r20012","location":"Intel/core i7/i7-7920hq · revision 20012 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7920hq&oldid=20012","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2181318ebbe98590","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6413-r20012","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-2181318ebbe98590"},{"id":"cw-2193cede18c37258","name":"Xeon Gold 6130T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6130t"],"fields":[{"key":"Model name","value":"Xeon Gold 6130T","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6130T","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303593000","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3J8","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1511-r4963","location":"Intel/xeon gold/6130t · revision 4963 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2193cede18c37258","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6130t&oldid=4963","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1511-r4963"],"url":"https://museum.vlsi.kr/objects/cw-2193cede18c37258"},{"id":"cw-21abf24e7296e444","name":"Ryzen 5 PRO 4650G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 5 pro 4650g"],"fields":[{"key":"Model name","value":"Ryzen 5 PRO 4650G","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 4650G","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000143","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000143MPK","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 21, 2020","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3700,"unit":"MHz","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1900,"unit":"MHz","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-8-r96924","location":"Amd/ryzen 5/pro 4650g · revision 96924 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-30. Not an independent measurement.","entityId":"cw-21abf24e7296e444","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%204650g&oldid=96924","sourceDate":"2022-11-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8-r96924"],"url":"https://museum.vlsi.kr/objects/cw-21abf24e7296e444"},{"id":"cw-21be4161235c477f","name":"AMD-K6-2/333AMZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-333amz"],"fields":[{"key":"Model name","value":"K6-2/333AMZ","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/333AMZ","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/333AMZ","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333.66,"unit":"MHz","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"95.33 MT/s","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.9,"unit":"V","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8373-r26068","location":"Amd/k6-2/k6-2-333amz · revision 26068 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21be4161235c477f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz&oldid=26068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8373-r26068"],"url":"https://museum.vlsi.kr/objects/cw-21be4161235c477f"},{"id":"cw-21c1efe3dd137b11","name":"A80286-6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"A80286","year":1985,"architecture":"80286","process":"1.5 µm","aliases":["Amd am286 a80286-6"],"fields":[{"key":"Model name","value":"A80286-6","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"A80286-6","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80286-6","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80286-6B","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1985,"unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1985,"unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"A80286","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":6,"unit":"MHz","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6 MT/s","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":134000,"unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":73,"unit":"mm²","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-68","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CPGA-68","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8608-r26806","location":"Amd/am286/a80286-6 · revision 26806 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21c1efe3dd137b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fa80286-6&oldid=26806","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8608-r26806"],"url":"https://museum.vlsi.kr/objects/cw-21c1efe3dd137b11"},{"id":"cw-21d3de92995cf050","name":"CN3005-500 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3000","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3005-500bg350-scp"],"fields":[{"key":"Model name","value":"Cavium CN3005-500 SCP","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3005-500 SCP","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3005-500BG350-SCP","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3000","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-350","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":24,"unit":"KiB","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1,017 MiB/s","unit":"","sourceId":"chipswiki-8276-r25936","location":"Cavium/octeon/cn3005-500bg350-scp · revision 25936 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-21d3de92995cf050","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-scp&oldid=25936","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8276-r25936"],"url":"https://museum.vlsi.kr/objects/cw-21d3de92995cf050"},{"id":"cw-21ef42dd8643b8b8","name":"Core i3-380M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-300","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i3 i3-380m"],"fields":[{"key":"Model name","value":"Intel Core i3-380M","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-380M","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617004116AH","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 26, 2010","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 26, 2010","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-300","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2533.33,"unit":"MHz","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBZX","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","alternatives":[{"value":"8 Gb","sourceId":"chipswiki-916-r2513","reason":"Intel/core i3/i3-380m · revision 2513 · {{memory controller}} / max mem. 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Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. 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Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. 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Not an independent measurement.","entityId":"cw-21ef42dd8643b8b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-380m&oldid=2513","sourceDate":"2020-10-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-916-r2513","location":"Intel/core i3/i3-380m · revision 2513 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-28. 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Not an independent measurement.","entityId":"cw-2218e09e17622f94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah%20ii&oldid=23832","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"VIA Technologies","unit":"","sourceId":"chipswiki-7371-r23832","location":"Via technologies/microarchitectures/isaiah ii · revision 23832 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. 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Not an independent measurement.","entityId":"cw-2218e09e17622f94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah%20ii&oldid=23832","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-7371-r23832","location":"Via technologies/microarchitectures/isaiah ii · revision 23832 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-2218e09e17622f94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah%20ii&oldid=23832","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-7371-r23832","location":"Via technologies/microarchitectures/isaiah ii · revision 23832 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-2218e09e17622f94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah%20ii&oldid=23832","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7371-r23832","location":"Via technologies/microarchitectures/isaiah ii · revision 23832 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-2218e09e17622f94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah%20ii&oldid=23832","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Isaiah","unit":"","sourceId":"chipswiki-7371-r23832","location":"Via technologies/microarchitectures/isaiah ii · revision 23832 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-2218e09e17622f94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah%20ii&oldid=23832","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"ZhangJiang","unit":"","sourceId":"chipswiki-7371-r23832","location":"Via technologies/microarchitectures/isaiah ii · revision 23832 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-2218e09e17622f94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah%20ii&oldid=23832","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7371-r23832"],"url":"https://museum.vlsi.kr/objects/cw-2218e09e17622f94"},{"id":"cw-22428e2f81b25d9c","name":"Exynos 5430","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 5","year":2014,"architecture":"Cortex-A15","process":"20 nm","aliases":["Samsung exynos 5430"],"fields":[{"key":"Model name","value":"Exynos 5430","unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5430,"unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Aug 13, 2014","unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"Aug 13, 2014","unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 5","unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1800,"unit":"MHz","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1300,"unit":"MHz","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A15","unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A15","unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A7","unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":20,"unit":"nm","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6847-r21337","location":"Samsung/exynos/5430 · revision 21337 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-22428e2f81b25d9c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5430&oldid=21337","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6847-r21337"],"url":"https://museum.vlsi.kr/objects/cw-22428e2f81b25d9c"},{"id":"cw-2273cfa37f17d636","name":"Ryzen 7 2800H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2800","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 7 2800h"],"fields":[{"key":"Model name","value":"Ryzen 7 2800H","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2800H","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YM2800C3T4MFB","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 10, 2018","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 10, 2018","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2800,"unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 11","unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":11,"unit":"","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-4835-r15639","location":"Amd/ryzen 7/2800h · revision 15639 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F2800h&oldid=15639","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FP5","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1140,"unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.7-1.0 mm","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":35,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.38,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-2273cfa37f17d636","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4835-r15639","chipswiki-31111-r91577"],"url":"https://museum.vlsi.kr/objects/cw-2273cfa37f17d636"},{"id":"cw-227f140eafe814e8","name":"Quicksilver","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Ampere Computing","year":2019,"process":"7 nm","aliases":["Ampere computing microarchitectures quicksilver"],"fields":[{"key":"Architecture name","value":"Quicksilver","unit":"","sourceId":"chipswiki-1069-r3087","location":"Ampere computing/microarchitectures/quicksilver · revision 3087 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-27. Not an independent measurement.","entityId":"cw-227f140eafe814e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Fmicroarchitectures%2Fquicksilver&oldid=3087","sourceDate":"2020-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Ampere Computing","unit":"","sourceId":"chipswiki-1069-r3087","location":"Ampere computing/microarchitectures/quicksilver · revision 3087 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-27. Not an independent measurement.","entityId":"cw-227f140eafe814e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Fmicroarchitectures%2Fquicksilver&oldid=3087","sourceDate":"2020-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1069-r3087","location":"Ampere computing/microarchitectures/quicksilver · revision 3087 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-27. Not an independent measurement.","entityId":"cw-227f140eafe814e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Fmicroarchitectures%2Fquicksilver&oldid=3087","sourceDate":"2020-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2019,"unit":"","sourceId":"chipswiki-1069-r3087","location":"Ampere computing/microarchitectures/quicksilver · revision 3087 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-27. Not an independent measurement.","entityId":"cw-227f140eafe814e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Fmicroarchitectures%2Fquicksilver&oldid=3087","sourceDate":"2020-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1069-r3087","location":"Ampere computing/microarchitectures/quicksilver · revision 3087 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-27. Not an independent measurement.","entityId":"cw-227f140eafe814e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Fmicroarchitectures%2Fquicksilver&oldid=3087","sourceDate":"2020-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-1069-r3087","location":"Ampere computing/microarchitectures/quicksilver · revision 3087 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-27. Not an independent measurement.","entityId":"cw-227f140eafe814e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Fmicroarchitectures%2Fquicksilver&oldid=3087","sourceDate":"2020-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-1069-r3087","location":"Ampere computing/microarchitectures/quicksilver · revision 3087 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-27. Not an independent measurement.","entityId":"cw-227f140eafe814e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Fmicroarchitectures%2Fquicksilver&oldid=3087","sourceDate":"2020-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Skylark","unit":"","sourceId":"chipswiki-1069-r3087","location":"Ampere computing/microarchitectures/quicksilver · revision 3087 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-27. Not an independent measurement.","entityId":"cw-227f140eafe814e8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ampere%20computing%2Fmicroarchitectures%2Fquicksilver&oldid=3087","sourceDate":"2020-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Mystique","unit":"","sourceId":"chipswiki-1069-r3087","location":"Ampere computing/microarchitectures/quicksilver · revision 3087 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-27. 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Not an independent measurement.","entityId":"cw-228e2a43d3199e5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320vc%5Cw&oldid=44717","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14656-r44717","location":"Amd/am186ex/am186em–20vc\\w · revision 44717 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-228e2a43d3199e5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320vc%5Cw&oldid=44717","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EM–20VC\\W","unit":"","sourceId":"chipswiki-14656-r44717","location":"Amd/am186ex/am186em–20vc\\w · revision 44717 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-228e2a43d3199e5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320vc%5Cw&oldid=44717","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14656-r44717","location":"Amd/am186ex/am186em–20vc\\w · revision 44717 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-228e2a43d3199e5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320vc%5Cw&oldid=44717","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14656-r44717","location":"Amd/am186ex/am186em–20vc\\w · revision 44717 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-228e2a43d3199e5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320vc%5Cw&oldid=44717","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14656-r44717","location":"Amd/am186ex/am186em–20vc\\w · revision 44717 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-228e2a43d3199e5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320vc%5Cw&oldid=44717","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186EM","unit":"","sourceId":"chipswiki-14656-r44717","location":"Amd/am186ex/am186em–20vc\\w · revision 44717 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-228e2a43d3199e5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320vc%5Cw&oldid=44717","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-14656-r44717","location":"Amd/am186ex/am186em–20vc\\w · revision 44717 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-228e2a43d3199e5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320vc%5Cw&oldid=44717","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"5 MT/s","unit":"","sourceId":"chipswiki-14656-r44717","location":"Amd/am186ex/am186em–20vc\\w · revision 44717 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-228e2a43d3199e5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320vc%5Cw&oldid=44717","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14656-r44717","location":"Amd/am186ex/am186em–20vc\\w · revision 44717 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-228e2a43d3199e5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320vc%5Cw&oldid=44717","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14656-r44717","location":"Amd/am186ex/am186em–20vc\\w · revision 44717 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-228e2a43d3199e5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320vc%5Cw&oldid=44717","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14656-r44717","location":"Amd/am186ex/am186em–20vc\\w · revision 44717 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-228e2a43d3199e5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320vc%5Cw&oldid=44717","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14656-r44717","location":"Amd/am186ex/am186em–20vc\\w · revision 44717 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-228e2a43d3199e5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320vc%5Cw&oldid=44717","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14656-r44717","location":"Amd/am186ex/am186em–20vc\\w · revision 44717 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-228e2a43d3199e5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320vc%5Cw&oldid=44717","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14656-r44717","location":"Amd/am186ex/am186em–20vc\\w · revision 44717 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-228e2a43d3199e5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320vc%5Cw&oldid=44717","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14656-r44717","location":"Amd/am186ex/am186em–20vc\\w · revision 44717 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-22dcf296246a98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215r&oldid=548","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-273-r548","location":"Intel/xeon silver/4215r · revision 548 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. 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Not an independent measurement.","entityId":"cw-22dcf296246a98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215r&oldid=548","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRGZE","unit":"","sourceId":"chipswiki-273-r548","location":"Intel/xeon silver/4215r · revision 548 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. 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Not an independent measurement.","entityId":"cw-22dcf296246a98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215r&oldid=548","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-273-r548","location":"Intel/xeon silver/4215r · revision 548 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. 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Not an independent measurement.","entityId":"cw-22dcf296246a98e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215r&oldid=548","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-273-r548","location":"Intel/xeon silver/4215r · revision 548 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. 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Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5740-900 SP","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5740-900BG1217-SP","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8179-r25838","location":"Cavium/octeon plus/cn5740-900bg1217-sp · revision 25838 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-900bg1217-sp&oldid=25838","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-22e28d6abf0f026a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8179-r25838","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-22e28d6abf0f026a"},{"id":"cw-2336f04dcffe53cf","name":"Ryzen 9 5900HX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 9 5900hx"],"fields":[{"key":"Model name","value":"Ryzen 9 5900HX","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5900HX","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000300","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 9","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4600,"unit":"MHz","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":2100,"unit":"MHz","sourceId":"chipswiki-722-r1732","location":"Amd/ryzen 9/5900hx · revision 1732 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-2336f04dcffe53cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900hx&oldid=1732","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-722-r1732"],"url":"https://museum.vlsi.kr/objects/cw-2336f04dcffe53cf"},{"id":"cw-235fb4dd8d8d845c","name":"Ocean Cove","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2022,"process":"10/7 nm","aliases":["Intel microarchitectures ocean cove"],"fields":[{"key":"Architecture name","value":"Ocean Cove","unit":"","sourceId":"chipswiki-908-r2443","location":"Intel/microarchitectures/ocean cove · revision 2443 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-16. Not an independent measurement.","entityId":"cw-235fb4dd8d8d845c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Focean%20cove&oldid=2443","sourceDate":"2020-11-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-908-r2443","location":"Intel/microarchitectures/ocean cove · revision 2443 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-16. Not an independent measurement.","entityId":"cw-235fb4dd8d8d845c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Focean%20cove&oldid=2443","sourceDate":"2020-11-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-908-r2443","location":"Intel/microarchitectures/ocean cove · revision 2443 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-16. Not an independent measurement.","entityId":"cw-235fb4dd8d8d845c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Focean%20cove&oldid=2443","sourceDate":"2020-11-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2022,"unit":"","sourceId":"chipswiki-908-r2443","location":"Intel/microarchitectures/ocean cove · revision 2443 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-16. Not an independent measurement.","entityId":"cw-235fb4dd8d8d845c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Focean%20cove&oldid=2443","sourceDate":"2020-11-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"10/7 nm","unit":"","sourceId":"chipswiki-908-r2443","location":"Intel/microarchitectures/ocean cove · revision 2443 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-16. Not an independent measurement.","entityId":"cw-235fb4dd8d8d845c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Focean%20cove&oldid=2443","sourceDate":"2020-11-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-908-r2443","location":"Intel/microarchitectures/ocean cove · revision 2443 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-16. Not an independent measurement.","entityId":"cw-235fb4dd8d8d845c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Focean%20cove&oldid=2443","sourceDate":"2020-11-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Golden Cove","unit":"","sourceId":"chipswiki-908-r2443","location":"Intel/microarchitectures/ocean cove · revision 2443 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-16. Not an independent measurement.","entityId":"cw-235fb4dd8d8d845c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Focean%20cove&oldid=2443","sourceDate":"2020-11-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-908-r2443"],"url":"https://museum.vlsi.kr/objects/cw-235fb4dd8d8d845c"},{"id":"cw-2376202b444baa65","name":"Shadowcat","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AppliedMicro","year":2013,"process":"28 nm","aliases":["Apm microarchitectures shadowcat"],"fields":[{"key":"Architecture name","value":"Shadowcat","unit":"","sourceId":"chipswiki-4774-r15403","location":"Apm/microarchitectures/shadowcat · revision 15403 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2376202b444baa65","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fshadowcat&oldid=15403","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AppliedMicro","unit":"","sourceId":"chipswiki-4774-r15403","location":"Apm/microarchitectures/shadowcat · revision 15403 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2376202b444baa65","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fshadowcat&oldid=15403","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4774-r15403","location":"Apm/microarchitectures/shadowcat · revision 15403 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2376202b444baa65","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fshadowcat&oldid=15403","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2013,"unit":"","sourceId":"chipswiki-4774-r15403","location":"Apm/microarchitectures/shadowcat · revision 15403 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2376202b444baa65","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fshadowcat&oldid=15403","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-4774-r15403","location":"Apm/microarchitectures/shadowcat · revision 15403 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2376202b444baa65","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fshadowcat&oldid=15403","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":8,"unit":"","sourceId":"chipswiki-4774-r15403","location":"Apm/microarchitectures/shadowcat · revision 15403 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2376202b444baa65","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fshadowcat&oldid=15403","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-4774-r15403","location":"Apm/microarchitectures/shadowcat · revision 15403 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2376202b444baa65","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fshadowcat&oldid=15403","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-4774-r15403","location":"Apm/microarchitectures/shadowcat · revision 15403 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2376202b444baa65","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fshadowcat&oldid=15403","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Storm","unit":"","sourceId":"chipswiki-4774-r15403","location":"Apm/microarchitectures/shadowcat · revision 15403 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2376202b444baa65","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fshadowcat&oldid=15403","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Skylark","unit":"","sourceId":"chipswiki-4774-r15403","location":"Apm/microarchitectures/shadowcat · revision 15403 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2376202b444baa65","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fshadowcat&oldid=15403","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4774-r15403"],"url":"https://museum.vlsi.kr/objects/cw-2376202b444baa65"},{"id":"cw-239197251fd3a1f4","name":"Xeon D-1541","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1541"],"fields":[{"key":"Model name","value":"Xeon D-1541","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1541","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.5 MiB","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-3734-r11441","location":"Intel/xeon d/d-1541 · revision 11441 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-239197251fd3a1f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1541&oldid=11441","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3734-r11441"],"url":"https://museum.vlsi.kr/objects/cw-239197251fd3a1f4"},{"id":"cw-239321001e5c5b8f","name":"Alchemy Au1000-266MCC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2001,"architecture":"Au1","process":"180 nm","aliases":["Alchemy au1000-266mcc"],"fields":[{"key":"Model name","value":"Alchemy Au1000-266MCC","unit":"","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1000-266MCC","unit":"","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. 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Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 13, 2000","unit":"","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. 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Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":266,"unit":"MHz","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"DA","unit":"","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HA","unit":"","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HB","unit":"","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HC","unit":"","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HD","unit":"","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / core stepping 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 5","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"core stepping 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. 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Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. 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Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. 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Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. 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Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.266 GB/s","unit":"","sourceId":"chipswiki-488-r972","location":"Alchemy/au1000-266mcc · revision 972 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-239321001e5c5b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mcc&oldid=972","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-488-r972"],"url":"https://museum.vlsi.kr/objects/cw-239321001e5c5b8f"},{"id":"cw-23a103931ee648ca","name":"Alchemy Au1550-500MBC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2004,"architecture":"Au1","aliases":["Alchemy au1550-500mbc"],"fields":[{"key":"Model name","value":"Alchemy Au1550-500MBC","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1550-500MBC","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1550-500MBCAA","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2004","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 2004","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AA","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1440 mW","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-166","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.333 GB/s","unit":"","sourceId":"chipswiki-461-r942","location":"Alchemy/au1550-500mbc · revision 942 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-23a103931ee648ca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbc&oldid=942","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-461-r942"],"url":"https://museum.vlsi.kr/objects/cw-23a103931ee648ca"},{"id":"cw-23a17e5866811fb2","name":"Xeon Platinum 8270","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 8270"],"fields":[{"key":"Model name","value":"Xeon Platinum 8270","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8270,"unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504195201","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF96","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8200,"unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":26,"unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":52,"unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.625,"unit":"MiB","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"26x32 KiB","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":832,"unit":"KiB","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"26x32 KiB","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":26,"unit":"MiB","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"26x1 MiB","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1458-r4905","location":"Intel/xeon platinum/8270 · revision 4905 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-23a17e5866811fb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8270&oldid=4905","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1458-r4905"],"url":"https://museum.vlsi.kr/objects/cw-23a17e5866811fb2"},{"id":"cw-23fcb8e5b31ed355","name":"Xeon W-2155","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-2000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon w w-2155"],"fields":[{"key":"Model name","value":"Xeon W-2155","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-2155","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303533703","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3LR","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 29, 2017","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 29, 2017","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-2000","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4500,"unit":"MHz","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-07-03. 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Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. 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Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Basin Falls","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake W","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. 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Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. 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Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. 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Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":10,"unit":"MiB","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x1 MiB","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":13.75,"unit":"MiB","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x1.375 MiB","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-2180-r7343","location":"Intel/xeon w/w-2155 · revision 7343 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-03. Not an independent measurement.","entityId":"cw-23fcb8e5b31ed355","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2155&oldid=7343","sourceDate":"2019-07-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2180-r7343"],"url":"https://museum.vlsi.kr/objects/cw-23fcb8e5b31ed355"},{"id":"cw-2421495714fb15aa","name":"NC4016","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Novix","year":1985,"process":"3 μm","aliases":["Novix nc4016"],"fields":[{"key":"Model name","value":"NC4016","unit":"","sourceId":"chipswiki-7673-r24950","location":"Novix/nc4016 · revision 24950 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2421495714fb15aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Novix%2Fnc4016&oldid=24950","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Novix","unit":"","sourceId":"chipswiki-7673-r24950","location":"Novix/nc4016 · revision 24950 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2421495714fb15aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Novix%2Fnc4016&oldid=24950","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"NC4016","unit":"","sourceId":"chipswiki-7673-r24950","location":"Novix/nc4016 · revision 24950 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2421495714fb15aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Novix%2Fnc4016&oldid=24950","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7673-r24950","location":"Novix/nc4016 · revision 24950 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2421495714fb15aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Novix%2Fnc4016&oldid=24950","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-7673-r24950","location":"Novix/nc4016 · revision 24950 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2421495714fb15aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Novix%2Fnc4016&oldid=24950","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 1985","unit":"","sourceId":"chipswiki-7673-r24950","location":"Novix/nc4016 · revision 24950 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2421495714fb15aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Novix%2Fnc4016&oldid=24950","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":7.5,"unit":"MHz","sourceId":"chipswiki-7673-r24950","location":"Novix/nc4016 · revision 24950 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2421495714fb15aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Novix%2Fnc4016&oldid=24950","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"3 μm","unit":"","sourceId":"chipswiki-7673-r24950","location":"Novix/nc4016 · revision 24950 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2421495714fb15aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Novix%2Fnc4016&oldid=24950","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":16000,"unit":"","sourceId":"chipswiki-7673-r24950","location":"Novix/nc4016 · revision 24950 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2421495714fb15aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Novix%2Fnc4016&oldid=24950","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7673-r24950","location":"Novix/nc4016 · revision 24950 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2421495714fb15aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Novix%2Fnc4016&oldid=24950","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-7673-r24950","location":"Novix/nc4016 · revision 24950 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2421495714fb15aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Novix%2Fnc4016&oldid=24950","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7673-r24950","location":"Novix/nc4016 · revision 24950 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2421495714fb15aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Novix%2Fnc4016&oldid=24950","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7673-r24950","location":"Novix/nc4016 · revision 24950 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2421495714fb15aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Novix%2Fnc4016&oldid=24950","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7673-r24950"],"url":"https://museum.vlsi.kr/objects/cw-2421495714fb15aa"},{"id":"cw-24374c594e86fef0","name":"AMD-K6-III/366AFK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III Mobile","year":1999,"architecture":"K6-III","process":"0.25 µm","aliases":["Amd k6-iii-p amd-k6-iii-366afk"],"fields":[{"key":"Model name","value":"AMD-K6-III/366AFK","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-III/366AFK","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-III/366AFK","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 31, 1999","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 31, 1999","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III-P","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III Mobile","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":366.66,"unit":"MHz","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sharptooth","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":9,"unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21300000,"unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":118,"unit":"mm²","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8308-r25998","location":"Amd/k6-iii-p/amd-k6-iii-366afk · revision 25998 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24374c594e86fef0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-366afk&oldid=25998","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8308-r25998"],"url":"https://museum.vlsi.kr/objects/cw-24374c594e86fef0"},{"id":"cw-2463d522982f9ef3","name":"Madison 9M","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2004,"process":"130 nm","aliases":["Intel microarchitectures madison 9m"],"fields":[{"key":"Architecture name","value":"Madison 9M","unit":"","sourceId":"chipswiki-8760-r27222","location":"Intel/microarchitectures/madison 9m · revision 27222 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-2463d522982f9ef3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmadison%209m&oldid=27222","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8760-r27222","location":"Intel/microarchitectures/madison 9m · revision 27222 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-2463d522982f9ef3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmadison%209m&oldid=27222","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8760-r27222","location":"Intel/microarchitectures/madison 9m · revision 27222 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-2463d522982f9ef3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmadison%209m&oldid=27222","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"November 8, 2004","unit":"","sourceId":"chipswiki-8760-r27222","location":"Intel/microarchitectures/madison 9m · revision 27222 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-2463d522982f9ef3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmadison%209m&oldid=27222","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8760-r27222","location":"Intel/microarchitectures/madison 9m · revision 27222 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-2463d522982f9ef3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmadison%209m&oldid=27222","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-8760-r27222","location":"Intel/microarchitectures/madison 9m · revision 27222 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-2463d522982f9ef3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmadison%209m&oldid=27222","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"IA-64","unit":"","sourceId":"chipswiki-8760-r27222","location":"Intel/microarchitectures/madison 9m · revision 27222 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-2463d522982f9ef3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmadison%209m&oldid=27222","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Madison","unit":"","sourceId":"chipswiki-8760-r27222","location":"Intel/microarchitectures/madison 9m · revision 27222 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-2463d522982f9ef3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmadison%209m&oldid=27222","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Montecito","unit":"","sourceId":"chipswiki-8760-r27222","location":"Intel/microarchitectures/madison 9m · revision 27222 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-2463d522982f9ef3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmadison%209m&oldid=27222","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Fanwood","unit":"","sourceId":"chipswiki-8760-r27222","location":"Intel/microarchitectures/madison 9m · revision 27222 · {{microarchitecture}} / successor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 2","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-2463d522982f9ef3","scope":"successor 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmadison%209m&oldid=27222","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8760-r27222"],"url":"https://museum.vlsi.kr/objects/cw-2463d522982f9ef3"},{"id":"cw-24699b33ee1c8edc","name":"Snapdragon 850","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","year":2018,"architecture":"Cortex-A75","process":"10 nm","aliases":["Qualcomm snapdragon 800 850"],"fields":[{"key":"Model name","value":"Snapdragon 850","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SDM850","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2018","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 5, 2018","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 800","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2960,"unit":"MHz","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A75","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 385 Gold","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 385 Silver","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":512,"unit":"KiB","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 1)","value":"4-way set associative","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 1)","value":"4-way set associative","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":1,"unit":"MiB","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"4x256 KiB","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 1)","value":"8-way set associative","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":512,"unit":"KiB","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":256,"unit":"KiB","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 2)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 2)","value":"2-way set associative","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":256,"unit":"KiB","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 2)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 2)","value":"4-way set associative","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":512,"unit":"KiB","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"4x128 KiB","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 2)","value":"8-way set associative","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":29.87,"unit":"GiB/s","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 630","unit":"","sourceId":"chipswiki-1657-r5750","location":"Qualcomm/snapdragon 800/850 · revision 5750 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-21. Not an independent measurement.","entityId":"cw-24699b33ee1c8edc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F850&oldid=5750","sourceDate":"2019-10-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1657-r5750"],"url":"https://museum.vlsi.kr/objects/cw-24699b33ee1c8edc"},{"id":"cw-246b8df1dc4ff989","name":"Core i3-6320T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-6000","year":null,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i3 6320t"],"fields":[{"key":"Model name","value":"Core i3-6320T","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-6320T","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201927003","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2HC","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 9, 2016","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-6000","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-246b8df1dc4ff989","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2F6320t&oldid=25601","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-8019-r25601","location":"Intel/core i3/6320t · revision 25601 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248b4e687d67c773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7320&oldid=25535","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7965-r25535","location":"Intel/core i3/i3-7320 · revision 25535 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4870&oldid=25067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7697-r25067","location":"Intel/xeon e7/e7-4870 · revision 25067 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4870&oldid=25067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":30,"unit":"MiB","sourceId":"chipswiki-7697-r25067","location":"Intel/xeon e7/e7-4870 · revision 25067 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4870&oldid=25067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x3 MiB","unit":"","sourceId":"chipswiki-7697-r25067","location":"Intel/xeon e7/e7-4870 · revision 25067 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4870&oldid=25067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7697-r25067","location":"Intel/xeon e7/e7-4870 · revision 25067 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4870&oldid=25067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7697-r25067","location":"Intel/xeon e7/e7-4870 · revision 25067 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4870&oldid=25067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7697-r25067","location":"Intel/xeon e7/e7-4870 · revision 25067 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4870&oldid=25067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7697-r25067","location":"Intel/xeon e7/e7-4870 · revision 25067 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4870&oldid=25067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7697-r25067","location":"Intel/xeon e7/e7-4870 · revision 25067 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4870&oldid=25067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.77,"unit":"GiB/s","sourceId":"chipswiki-7697-r25067","location":"Intel/xeon e7/e7-4870 · revision 25067 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4870&oldid=25067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-8","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1567,"unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":56.4,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.2,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-248e931e806cfcfd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7697-r25067","chipswiki-31576-r92962"],"url":"https://museum.vlsi.kr/objects/cw-248e931e806cfcfd"},{"id":"cw-24b6a39752e447c2","name":"POWER6","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2007,"process":"65 nm","aliases":["Ibm microarchitectures power6"],"fields":[{"key":"Architecture name","value":"POWER6","unit":"","sourceId":"chipswiki-9921-r31545","location":"Ibm/microarchitectures/power6 · revision 31545 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. 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Not an independent measurement.","entityId":"cw-24b6a39752e447c2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower6&oldid=31545","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-9921-r31545","location":"Ibm/microarchitectures/power6 · revision 31545 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-24b6a39752e447c2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower6&oldid=31545","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2007,"unit":"","sourceId":"chipswiki-9921-r31545","location":"Ibm/microarchitectures/power6 · revision 31545 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. 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Not an independent measurement.","entityId":"cw-24b7e82104858b6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086b&oldid=26696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8503-r26696","location":"Amd/am8086/j8086b · revision 26696 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-24b7e82104858b6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086b&oldid=26696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8503-r26696","location":"Amd/am8086/j8086b · revision 26696 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24b7e82104858b6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086b&oldid=26696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8503-r26696","location":"Amd/am8086/j8086b · revision 26696 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-24b7e82104858b6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086b&oldid=26696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8503-r26696","location":"Amd/am8086/j8086b · revision 26696 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-24b7e82104858b6e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086b&oldid=26696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8503-r26696","location":"Amd/am8086/j8086b · revision 26696 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SDM855AC","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"SM8150-AC","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 15, 2019","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"Q3, 2019","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 800","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1800,"unit":"MHz","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2420,"unit":"MHz","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":2960,"unit":"MHz","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A76","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 485 Gold","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 485 Silver","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":6700000000,"unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":73.27,"unit":"mm²","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. 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Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":512,"unit":"KiB","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 1)","value":"4-way set associative","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 1)","value":"4-way set associative","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-17. 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Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"4x256 KiB","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-07-17. 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Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 2)","value":"4-way set associative","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":512,"unit":"KiB","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"4x128 KiB","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 2)","value":"8-way set associative","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-07-17. 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Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. Not an independent measurement.","entityId":"cw-24d7631d475fd6af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F855%20plus&oldid=571","sourceDate":"2022-07-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 640 GPU","unit":"","sourceId":"chipswiki-284-r571","location":"Qualcomm/snapdragon 800/855 plus · revision 571 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-17. 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Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. 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Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9980-2400LG4077-Y21-G","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-11-29. 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Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"ThunderX2","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2000,"unit":"MHz","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2100,"unit":"MHz","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":2200,"unit":"MHz","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 4","value":2300,"unit":"MHz","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / frequency 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 4","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"Multiple clock domains; raw parameter frequency 4","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 5","value":2400,"unit":"MHz","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / frequency 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 5","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"Multiple clock domains; raw parameter frequency 5","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 6","value":2500,"unit":"MHz","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / frequency 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 6","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"Multiple clock domains; raw parameter frequency 6","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.1","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Vulcan","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":128,"unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32x256 KiB","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"32x1 MiB","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-1600-r5356","location":"Cavium/thunderx2/cn9980 · revision 5356 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-29. Not an independent measurement.","entityId":"cw-24daa1b554ddbbc5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9980&oldid=5356","sourceDate":"2019-11-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1600-r5356"],"url":"https://museum.vlsi.kr/objects/cw-24daa1b554ddbbc5"},{"id":"cw-24eeeaaf2ec1ad4a","name":"NetBurst","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2000,"process":"180 nm","aliases":["Intel microarchitectures netburst (client)"],"fields":[{"key":"Architecture name","value":"NetBurst","unit":"","sourceId":"chipswiki-4987-r16133","location":"Intel/microarchitectures/netburst (client) · revision 16133 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-24eeeaaf2ec1ad4a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnetburst%20(client)&oldid=16133","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4987-r16133","location":"Intel/microarchitectures/netburst (client) · revision 16133 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-24eeeaaf2ec1ad4a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnetburst%20(client)&oldid=16133","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4987-r16133","location":"Intel/microarchitectures/netburst (client) · revision 16133 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-24eeeaaf2ec1ad4a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnetburst%20(client)&oldid=16133","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"November 20, 2000","unit":"","sourceId":"chipswiki-4987-r16133","location":"Intel/microarchitectures/netburst (client) · revision 16133 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-24eeeaaf2ec1ad4a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnetburst%20(client)&oldid=16133","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-4987-r16133","location":"Intel/microarchitectures/netburst (client) · revision 16133 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-24eeeaaf2ec1ad4a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnetburst%20(client)&oldid=16133","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-4987-r16133","location":"Intel/microarchitectures/netburst (client) · revision 16133 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-24eeeaaf2ec1ad4a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnetburst%20(client)&oldid=16133","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"P6","unit":"","sourceId":"chipswiki-4987-r16133","location":"Intel/microarchitectures/netburst (client) · revision 16133 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-24eeeaaf2ec1ad4a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnetburst%20(client)&oldid=16133","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Enhanced NetBurst","unit":"","sourceId":"chipswiki-4987-r16133","location":"Intel/microarchitectures/netburst (client) · revision 16133 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-24eeeaaf2ec1ad4a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnetburst%20(client)&oldid=16133","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-4987-r16133","location":"Intel/microarchitectures/netburst (client) · revision 16133 · {{microarchitecture}} / successor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 2","note":"Source-reported parameter; source revision 2018-08-26. Not an independent measurement.","entityId":"cw-24eeeaaf2ec1ad4a","scope":"successor 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnetburst%20(client)&oldid=16133","sourceDate":"2018-08-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4987-r16133"],"url":"https://museum.vlsi.kr/objects/cw-24eeeaaf2ec1ad4a"},{"id":"cw-250e1e36201caf97","name":"VY86C061","kind":"sku","entityType":"product-model","subtype":"soc","company":"Arm","year":1993,"architecture":"ARM6","process":"0.8 µm","aliases":["Vti vl86cx vy86c061"],"fields":[{"key":"Model name","value":"VY86C061","unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"VY86C061","unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C061-20FC","unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C061-25FC","unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1993,"unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"VL86Cx","unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":20,"unit":"MHz","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":25,"unit":"MHz","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv3","unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM6","unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MEMC","unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM60","unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.8,"unit":"µm","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":35530,"unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":5.89,"unit":"mm²","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"","sourceId":"chipswiki-7628-r24883","location":"Vti/vl86cx/vy86c061 · revision 24883 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c061&oldid=24883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-84","unit":"","sourceId":"chipswiki-31441-r92366","location":"Template:Packages/vti/plcc-84 · revision 92366 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-84&oldid=92366","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-31441-r92366","location":"Template:Packages/vti/plcc-84 · revision 92366 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-84&oldid=92366","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31441-r92366","location":"Template:Packages/vti/plcc-84 · revision 92366 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-84&oldid=92366","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":29.41,"unit":"mm","sourceId":"chipswiki-31441-r92366","location":"Template:Packages/vti/plcc-84 · revision 92366 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-84&oldid=92366","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":30.35,"unit":"mm","sourceId":"chipswiki-31441-r92366","location":"Template:Packages/vti/plcc-84 · revision 92366 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-84&oldid=92366","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":5.08,"unit":"mm","sourceId":"chipswiki-31441-r92366","location":"Template:Packages/vti/plcc-84 · revision 92366 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-250e1e36201caf97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-84&oldid=92366","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7628-r24883","chipswiki-31441-r92366"],"url":"https://museum.vlsi.kr/objects/cw-250e1e36201caf97"},{"id":"cw-2573fbd2028f4ec9","name":"Xeon D-1540","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1540"],"fields":[{"key":"Model name","value":"Xeon D-1540","unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1540","unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067401635553","unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR29A","unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 9, 2015","unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 9, 2015","unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2600,"unit":"MHz","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-2573fbd2028f4ec9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1540&oldid=11439","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3733-r11439","location":"Intel/xeon d/d-1540 · revision 11439 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080A-4CC","unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080A-4CC","unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":4,"unit":"MHz","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8474-r26667","location":"Amd/am9080/am9080a-4cc · revision 26667 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-257e5e3ff291b8b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4cc&oldid=26667","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8474-r26667"],"url":"https://museum.vlsi.kr/objects/cw-257e5e3ff291b8b5"},{"id":"cw-25aa425c8bf515e1","name":"AMD-K6-2/333AMZ-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-333amz-66"],"fields":[{"key":"Model name","value":"K6-2/333AMZ-66","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/333AMZ-66","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/333AMZ-66","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333.33,"unit":"MHz","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.9,"unit":"V","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8372-r26067","location":"Amd/k6-2/k6-2-333amz-66 · revision 26067 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25aa425c8bf515e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333amz-66&oldid=26067","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8372-r26067"],"url":"https://museum.vlsi.kr/objects/cw-25aa425c8bf515e1"},{"id":"cw-25ac17db6739cd2e","name":"Core i7-680UM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-600","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i7 i7-680um"],"fields":[{"key":"Model name","value":"Intel Core i7-680UM","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-680UM","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617004860AA","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 27, 2010","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 27, 2010","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-600","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1466.66,"unit":"MHz","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2133.33,"unit":"MHz","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBST","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":166,"unit":"MHz","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":500,"unit":"MHz","sourceId":"chipswiki-7837-r25330","location":"Intel/core i7/i7-680um · revision 25330 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-680um&oldid=25330","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-25ac17db6739cd2e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-7946-r25494","location":"Intel/core i5/i5-2560lm · revision 25494 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25cfed7b02704cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560lm&oldid=25494","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1017&oldid=25759","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-8100-r25759","location":"Freescale/qoriq/p1017 · revision 25759 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1017&oldid=25759","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-8100-r25759","location":"Freescale/qoriq/p1017 · revision 25759 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1017&oldid=25759","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P1017","unit":"","sourceId":"chipswiki-8100-r25759","location":"Freescale/qoriq/p1017 · revision 25759 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1017&oldid=25759","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8100-r25759","location":"Freescale/qoriq/p1017 · revision 25759 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1017&oldid=25759","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-8100-r25759","location":"Freescale/qoriq/p1017 · revision 25759 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1017&oldid=25759","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-8100-r25759","location":"Freescale/qoriq/p1017 · revision 25759 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1017&oldid=25759","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8100-r25759","location":"Freescale/qoriq/p1017 · revision 25759 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1017&oldid=25759","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8100-r25759","location":"Freescale/qoriq/p1017 · revision 25759 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1017&oldid=25759","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8100-r25759","location":"Freescale/qoriq/p1017 · revision 25759 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1017&oldid=25759","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8100-r25759","location":"Freescale/qoriq/p1017 · revision 25759 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1017&oldid=25759","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8100-r25759","location":"Freescale/qoriq/p1017 · revision 25759 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1017&oldid=25759","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TE-PBGA-457","unit":"","sourceId":"chipswiki-31377-r92173","location":"Template:Packages/freescale/te-pbga-457 · revision 92173 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-457&oldid=92173","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TE-PBGA","unit":"","sourceId":"chipswiki-31377-r92173","location":"Template:Packages/freescale/te-pbga-457 · revision 92173 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-457&oldid=92173","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":457,"unit":"","sourceId":"chipswiki-31377-r92173","location":"Template:Packages/freescale/te-pbga-457 · revision 92173 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-457&oldid=92173","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":19,"unit":"mm","sourceId":"chipswiki-31377-r92173","location":"Template:Packages/freescale/te-pbga-457 · revision 92173 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-457&oldid=92173","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":19,"unit":"mm","sourceId":"chipswiki-31377-r92173","location":"Template:Packages/freescale/te-pbga-457 · revision 92173 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e23610fa473253","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-457&oldid=92173","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8100-r25759","chipswiki-31377-r92173"],"url":"https://museum.vlsi.kr/objects/cw-25e23610fa473253"},{"id":"cw-25e360079cf539bc","name":"VY86C610","kind":"sku","entityType":"product-model","subtype":"soc","company":"Arm","year":1993,"architecture":"ARM6","process":"0.8 µm","aliases":["Vti vl86cx vy86c610"],"fields":[{"key":"Model name","value":"VY86C610","unit":"","sourceId":"chipswiki-7627-r24882","location":"Vti/vl86cx/vy86c610 · revision 24882 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e360079cf539bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610&oldid=24882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-7627-r24882","location":"Vti/vl86cx/vy86c610 · revision 24882 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e360079cf539bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610&oldid=24882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-7627-r24882","location":"Vti/vl86cx/vy86c610 · revision 24882 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e360079cf539bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610&oldid=24882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"VY86C610","unit":"","sourceId":"chipswiki-7627-r24882","location":"Vti/vl86cx/vy86c610 · revision 24882 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e360079cf539bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610&oldid=24882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C61020BC","unit":"","sourceId":"chipswiki-7627-r24882","location":"Vti/vl86cx/vy86c610 · revision 24882 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e360079cf539bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610&oldid=24882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C610-25","unit":"","sourceId":"chipswiki-7627-r24882","location":"Vti/vl86cx/vy86c610 · revision 24882 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e360079cf539bc","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610&oldid=24882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7627-r24882","location":"Vti/vl86cx/vy86c610 · revision 24882 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e360079cf539bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610&oldid=24882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1993,"unit":"","sourceId":"chipswiki-7627-r24882","location":"Vti/vl86cx/vy86c610 · revision 24882 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e360079cf539bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610&oldid=24882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"VL86Cx","unit":"","sourceId":"chipswiki-7627-r24882","location":"Vti/vl86cx/vy86c610 · revision 24882 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e360079cf539bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610&oldid=24882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":20,"unit":"MHz","sourceId":"chipswiki-7627-r24882","location":"Vti/vl86cx/vy86c610 · revision 24882 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e360079cf539bc","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c610&oldid=24882","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":25,"unit":"MHz","sourceId":"chipswiki-7627-r24882","location":"Vti/vl86cx/vy86c610 · revision 24882 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8830&oldid=25066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.35,"unit":"V","sourceId":"chipswiki-7696-r25066","location":"Intel/xeon e7/e7-8830 · revision 25066 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8830&oldid=25066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-7696-r25066","location":"Intel/xeon e7/e7-8830 · revision 25066 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8830&oldid=25066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-7696-r25066","location":"Intel/xeon e7/e7-8830 · revision 25066 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8830&oldid=25066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7696-r25066","location":"Intel/xeon e7/e7-8830 · revision 25066 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8830&oldid=25066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24,"unit":"MiB","sourceId":"chipswiki-7696-r25066","location":"Intel/xeon e7/e7-8830 · revision 25066 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8830&oldid=25066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x3 MiB","unit":"","sourceId":"chipswiki-7696-r25066","location":"Intel/xeon e7/e7-8830 · revision 25066 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8830&oldid=25066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7696-r25066","location":"Intel/xeon e7/e7-8830 · revision 25066 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8830&oldid=25066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7696-r25066","location":"Intel/xeon e7/e7-8830 · revision 25066 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8830&oldid=25066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7696-r25066","location":"Intel/xeon e7/e7-8830 · revision 25066 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8830&oldid=25066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7696-r25066","location":"Intel/xeon e7/e7-8830 · revision 25066 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8830&oldid=25066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7696-r25066","location":"Intel/xeon e7/e7-8830 · revision 25066 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8830&oldid=25066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.77,"unit":"GiB/s","sourceId":"chipswiki-7696-r25066","location":"Intel/xeon e7/e7-8830 · revision 25066 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8830&oldid=25066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-8","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1567,"unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":56.4,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.2,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-25e41ec59fc0458e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7696-r25066","chipswiki-31576-r92962"],"url":"https://museum.vlsi.kr/objects/cw-25e41ec59fc0458e"},{"id":"cw-260fe3e37ce7554c","name":"Am486DX2-66NV8T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2V","year":1995,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx2-66nv8t"],"fields":[{"key":"Model name","value":"Am486DX2-66NV8T","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX2-66NV8T","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-66NV8T","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 1995","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2V","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":66,"unit":"MHz","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX4V","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8566-r26764","location":"Amd/am486/am486dx2-66nv8t · revision 26764 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-260fe3e37ce7554c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66nv8t&oldid=26764","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8566-r26764"],"url":"https://museum.vlsi.kr/objects/cw-260fe3e37ce7554c"},{"id":"cw-26915424b0bc5dfc","name":"EPYC 7401P","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7000","year":2017,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc 7401p"],"fields":[{"key":"Model name","value":"EPYC 7401P","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7401P","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PS740PBEVHCAF","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7000,"unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Naples","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":19200000000,"unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":155,"unit":"W","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2.25,"unit":"MiB","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x64 KiB","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x512 KiB","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x8 MiB","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-5074-r16546","location":"Amd/epyc/7401p · revision 16546 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7401p&oldid=16546","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-4094","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket SP3","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-26915424b0bc5dfc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5074-r16546","chipswiki-31468-r92417"],"url":"https://museum.vlsi.kr/objects/cw-26915424b0bc5dfc"},{"id":"cw-26951d0bd6533483","name":"Xeon Platinum 8268","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 8268"],"fields":[{"key":"Model name","value":"Xeon Platinum 8268","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8268,"unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504195101","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF95","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8200,"unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1459-r4906","location":"Intel/xeon platinum/8268 · revision 4906 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-26951d0bd6533483","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8268&oldid=4906","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1459-r4906"],"url":"https://museum.vlsi.kr/objects/cw-26951d0bd6533483"},{"id":"cw-26a0dbe64630b6b8","name":"Celeron B810","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron b810"],"fields":[{"key":"Model name","value":"Celeron B810","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"B810","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700848800","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR088","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 14, 2011","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 14, 2011","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-6928-r21614","location":"Intel/celeron/b810 · revision 21614 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810&oldid=21614","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-26a0dbe64630b6b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"X704-466","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 1997","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"X704","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":466,"unit":"MHz","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"60x bus","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"X704","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"CHRP","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2700000,"unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"BiCMOS","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":150,"unit":"mm²","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.6,"unit":"V","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CBGA-359","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CBGA","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-359","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"KiB","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x2 KiB","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"direct mapped","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"KiB","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x2 KiB","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"direct mapped","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"KiB","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8111-r25770","location":"Exponential technology/x704/466 · revision 25770 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26d9dbcd0a02aaaa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F466&oldid=25770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8111-r25770"],"url":"https://museum.vlsi.kr/objects/cw-26d9dbcd0a02aaaa"},{"id":"cw-26dba1a29806bff9","name":"Celeron U3600","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P3000","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel celeron u3600"],"fields":[{"key":"Model name","value":"Intel Celeron U3600","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"U3600","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617005199AB","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 11, 2011","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 11, 2011","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P3000","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1199.99,"unit":"MHz","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBSP","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":166,"unit":"MHz","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":500,"unit":"MHz","sourceId":"chipswiki-8021-r25603","location":"Intel/celeron/u3600 · revision 25603 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3600&oldid=25603","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-26dba1a29806bff9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8021-r25603","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-26dba1a29806bff9"},{"id":"cw-272ecd4d609f3895","name":"Sea Islands","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":2013,"process":"28 nm","aliases":["Amd microarchitectures sea islands"],"fields":[{"key":"Architecture name","value":"Sea Islands","unit":"","sourceId":"chipswiki-13195-r38540","location":"Amd/microarchitectures/sea islands · revision 38540 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-21. Not an independent measurement.","entityId":"cw-272ecd4d609f3895","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsea%20islands&oldid=38540","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-13195-r38540","location":"Amd/microarchitectures/sea islands · revision 38540 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-21. Not an independent measurement.","entityId":"cw-272ecd4d609f3895","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsea%20islands&oldid=38540","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-13195-r38540","location":"Amd/microarchitectures/sea islands · revision 38540 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-21. Not an independent measurement.","entityId":"cw-272ecd4d609f3895","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsea%20islands&oldid=38540","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2013,"unit":"","sourceId":"chipswiki-13195-r38540","location":"Amd/microarchitectures/sea islands · revision 38540 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-21. Not an independent measurement.","entityId":"cw-272ecd4d609f3895","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsea%20islands&oldid=38540","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-13195-r38540","location":"Amd/microarchitectures/sea islands · revision 38540 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-21. Not an independent measurement.","entityId":"cw-272ecd4d609f3895","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsea%20islands&oldid=38540","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Southern Islands","unit":"","sourceId":"chipswiki-13195-r38540","location":"Amd/microarchitectures/sea islands · revision 38540 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-21. Not an independent measurement.","entityId":"cw-272ecd4d609f3895","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsea%20islands&oldid=38540","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Volcanic Islands","unit":"","sourceId":"chipswiki-13195-r38540","location":"Amd/microarchitectures/sea islands · revision 38540 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-21. Not an independent measurement.","entityId":"cw-272ecd4d609f3895","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsea%20islands&oldid=38540","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-13195-r38540"],"url":"https://museum.vlsi.kr/objects/cw-272ecd4d609f3895"},{"id":"cw-2731685eee53159f","name":"Xeon E-2144G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2144g"],"fields":[{"key":"Model name","value":"Xeon E-2144G","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. 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Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2144G","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403654220","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3WM","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. 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Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 12, 2018","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2000","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. 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Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4500,"unit":"MHz","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-25. 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Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. 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Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":71,"unit":"W","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics P630","unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. 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Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-3031-r10098","location":"Intel/xeon e/e-2144g · revision 10098 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-2731685eee53159f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2144g&oldid=10098","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3031-r10098"],"url":"https://museum.vlsi.kr/objects/cw-2731685eee53159f"},{"id":"cw-2739c1bedec6a333","name":"Xeon Silver 4208","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon silver 4208"],"fields":[{"key":"Model name","value":"Xeon Silver 4208","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":4208,"unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069503956401","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806954208","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFBM","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. 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Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4200,"unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R1","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. 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Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. 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Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-940-r2633","location":"Intel/xeon silver/4208 · revision 2633 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-2739c1bedec6a333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4208&oldid=2633","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-940-r2633"],"url":"https://museum.vlsi.kr/objects/cw-2739c1bedec6a333"},{"id":"cw-279001ae2d026ae0","name":"Core i7-6560U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-6560u"],"fields":[{"key":"Model name","value":"Core i7-6560U","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6560U","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066202496507","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2JB","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K1","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Graphics 540","unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-7847-r25345","location":"Intel/core i7/i7-6560u · revision 25345 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-279001ae2d026ae0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7847-r25345","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-279001ae2d026ae0"},{"id":"cw-27aed80d12cfcb29","name":"Core i5-540M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-500","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i5 i5-540m"],"fields":[{"key":"Model name","value":"Intel Core i5-540M","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-540M","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80617I5540M","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617004116AD","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617004116AD","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-500","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2533.33,"unit":"MHz","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3066.66,"unit":"MHz","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-03-31. 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Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBPF","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2020-03-31. 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Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBTV","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2020-03-31. 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Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. 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Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. 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Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-03-31. 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Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. 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Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. Not an independent measurement.","entityId":"cw-27aed80d12cfcb29","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540m&oldid=3818","sourceDate":"2020-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-1220-r3818","location":"Intel/core i5/i5-540m · revision 3818 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-31. 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Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6700TE","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2LP","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7840-r25333","location":"Intel/core i7/i7-6700te · revision 25333 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700te&oldid=25333","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-27fb24e3343abef4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7840-r25333","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-27fb24e3343abef4"},{"id":"cw-28082460d6d497a0","name":"Exynos 7270","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 7","year":2016,"architecture":"Cortex-A53","process":"14 nm","aliases":["Samsung exynos 7270"],"fields":[{"key":"Model name","value":"Exynos 7270","unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7270,"unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Octoer 11, 2016","unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"Octoer 11, 2016","unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 7","unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6845-r21332","location":"Samsung/exynos/7270 · revision 21332 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-28082460d6d497a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7270&oldid=21332","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6845-r21332"],"url":"https://museum.vlsi.kr/objects/cw-28082460d6d497a0"},{"id":"cw-281e2856f8c22499","name":"StrongARM","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"DEC","year":1996,"process":"0.35 µm","aliases":["Dec microarchitectures strongarm"],"fields":[{"key":"Architecture name","value":"StrongARM","unit":"","sourceId":"chipswiki-5291-r17297","location":"Dec/microarchitectures/strongarm · revision 17297 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-281e2856f8c22499","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Fstrongarm&oldid=17297","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"DEC","unit":"","sourceId":"chipswiki-5291-r17297","location":"Dec/microarchitectures/strongarm · revision 17297 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-281e2856f8c22499","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Fstrongarm&oldid=17297","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"DEC","unit":"","sourceId":"chipswiki-5291-r17297","location":"Dec/microarchitectures/strongarm · revision 17297 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-281e2856f8c22499","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Fstrongarm&oldid=17297","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5291-r17297","location":"Dec/microarchitectures/strongarm · revision 17297 · {{microarchitecture}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-281e2856f8c22499","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Fstrongarm&oldid=17297","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"February 5, 1996","unit":"","sourceId":"chipswiki-5291-r17297","location":"Dec/microarchitectures/strongarm · revision 17297 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-281e2856f8c22499","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Fstrongarm&oldid=17297","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.35,"unit":"µm","sourceId":"chipswiki-5291-r17297","location":"Dec/microarchitectures/strongarm · revision 17297 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-281e2856f8c22499","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Fstrongarm&oldid=17297","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-5291-r17297","location":"Dec/microarchitectures/strongarm · revision 17297 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-281e2856f8c22499","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Fstrongarm&oldid=17297","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":5,"unit":"","sourceId":"chipswiki-5291-r17297","location":"Dec/microarchitectures/strongarm · revision 17297 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-281e2856f8c22499","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Fstrongarm&oldid=17297","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"1-way","unit":"","sourceId":"chipswiki-5291-r17297","location":"Dec/microarchitectures/strongarm · revision 17297 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-281e2856f8c22499","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Fstrongarm&oldid=17297","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv4","unit":"","sourceId":"chipswiki-5291-r17297","location":"Dec/microarchitectures/strongarm · revision 17297 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-281e2856f8c22499","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Fstrongarm&oldid=17297","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"XScale","unit":"","sourceId":"chipswiki-5291-r17297","location":"Dec/microarchitectures/strongarm · revision 17297 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-281e2856f8c22499","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Fstrongarm&oldid=17297","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5291-r17297"],"url":"https://museum.vlsi.kr/objects/cw-281e2856f8c22499"}],"sources":[{"id":"chipwise-source-e3b5429e7023","title":"Disassembled Cubot smartphone — Chipwise image source","url":"https://chipwise.tech/fullsizeoutput_1eae-1000x750/","publisher":"Chipwise / NanoPhysics","published":null,"accessed":"2026-09-09","evidenceClass":"third-party-report","type":"photography","status":"image identity documented; used with permission"},{"id":"chipswiki-452-r933","title":"Alchemy Au1200-500MGC — ChipsWiki, revision 933","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-500mgc&oldid=933","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/thunderx2/cn9980"],"contentSha256":"2d7cab4cd58153c1e28e6514d7a2b185564b12f4fca8d4da6bd15c3af9e819de"},{"id":"chipswiki-4333-r13946","title":"ThunderX2 CN9970 — ChipsWiki, revision 13946","url":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9970&oldid=13946","publisher":"ChipsWiki / WikiChip contributors","published":"2018-12-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Dec/microarchitectures/strongarm"],"contentSha256":"e0d647ea26af5b8ad71465dbf17898628db26eb832d27650bdcb77dc0e7e8e71"},{"id":"chipswiki-7328-r23631","title":"Joshua — ChipsWiki, revision 23631","url":"https://chipswiki.org/index.php?title=Cyrix%2Fmicroarchitectures%2Fjoshua&oldid=23631","publisher":"ChipsWiki / WikiChip contributors","published":"2018-01-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-6442eq"],"contentSha256":"8c3d27378dc3ebf19a7987a6a5bb993c3ea3dc739d2cfa9b4148ff8bffdc7d40"},{"id":"chipswiki-2841-r9525","title":"Core i5-9400T — ChipsWiki, revision 9525","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400t&oldid=9525","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i5/i5-8550"],"contentSha256":"d7067672634731a384c2e8f622e71edee9de6efd0eb77a9e90e72228be123acf"},{"id":"chipswiki-7893-r25397","title":"Core i7-2637M — ChipsWiki, revision 25397","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2637m&oldid=25397","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2637m"],"contentSha256":"75ea45cd9ede761d3040c5974e4773b3a87a670daa284d713112490339bca64c"},{"id":"chipswiki-31408-r92251","title":"Template:Packages/intel/fcbga-1224 — revision 92251","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","publisher":"ChipsWiki / WikiChip contributors","published":"2017-09-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-1224"],"contentSha256":"6c882a72b40b8ddb66e582c17b09dc73287a46af805625092c703e3a491ab32f"},{"id":"chipswiki-7899-r25403","title":"Core i7-2617M — ChipsWiki, revision 25403","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2617m&oldid=25403","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2617m"],"contentSha256":"d289d9d79de35b314d4050e3fb71b5e96a770ee09f6d334efc8f374808d6503c"},{"id":"chipswiki-7847-r25345","title":"Core i7-6560U — ChipsWiki, revision 25345","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6560u&oldid=25345","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-620um"],"contentSha256":"0474763e62e003234e8691dadb8fd8445cc6122147d3c0632694e329100aa31f"},{"id":"chipswiki-7862-r25363","title":"Core i7-5500DU — ChipsWiki, revision 25363","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5500du&oldid=25363","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-5500du"],"contentSha256":"26d19331d5da7925e5e3f6344280956af45185b9c32a3d45e3f937c3d62fc5eb"},{"id":"chipswiki-7870-r25373","title":"Core i7-4770HQ — ChipsWiki, revision 25373","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770hq&oldid=25373","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-4770hq"],"contentSha256":"f2d823c12ebffb56da4620c63c5ac8d3d5476a76e6cfe33cd2e62432c146e166"},{"id":"chipswiki-7875-r25379","title":"Core i7-2760QM — ChipsWiki, revision 25379","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2760qm&oldid=25379","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2760qm"],"contentSha256":"321157420aad911942c8360adbe33a2a89501edbfd5e3d45796c34c442ffd799"},{"id":"chipswiki-7879-r25383","title":"Core i7-2710QE — ChipsWiki, revision 25383","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2710qe&oldid=25383","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/gen1"],"contentSha256":"222b3e2a10a40a08259d280f1eaf47e9c18708439d8353cd509450c70078014d"},{"id":"chipswiki-201-r402","title":"Sunny Cove — ChipsWiki, revision 402","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsunny%20cove&oldid=402","publisher":"ChipsWiki / WikiChip contributors","published":"2022-09-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/merced"],"contentSha256":"86cc44067e9748b181d1b48bd81936bec0499baa0d22b896b66ca472efa4ec13"},{"id":"chipswiki-908-r2443","title":"Ocean Cove — ChipsWiki, revision 2443","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Focean%20cove&oldid=2443","publisher":"ChipsWiki / WikiChip contributors","published":"2020-11-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/ocean_cove"],"contentSha256":"c156d464c1fd43ed18dfe711a6dff385f047f9bf1101d1024ff15a609e3dbce0"},{"id":"chipswiki-1172-r3651","title":"Ivy Bridge — ChipsWiki, revision 3651","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fivy%20bridge%20(client)&oldid=3651","publisher":"ChipsWiki / WikiChip contributors","published":"2020-05-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/ivy_bridge_(client)"],"contentSha256":"c1786a9fcb3694330033d77496ddf603a92029de5eec0ea3978bae6b826c678c"},{"id":"chipswiki-1825-r6144","title":"Silvermont — ChipsWiki, revision 6144","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsilvermont&oldid=6144","publisher":"ChipsWiki / WikiChip contributors","published":"2019-09-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/silvermont"],"contentSha256":"55d5f9a73551b52e6f1abceb569b36b039f103928986b215d5d37be88d3e5f46"},{"id":"chipswiki-2503-r8586","title":"Polaris — ChipsWiki, revision 8586","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpolaris&oldid=8586","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/polaris"],"contentSha256":"2e94d781fa46c2101eb9a6939b326e5b9d17a17f6994753fe7ba36c7d01302cf"},{"id":"chipswiki-3041-r10167","title":"Pentium M — ChipsWiki, revision 10167","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpentium%20m&oldid=10167","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/pentium_m"],"contentSha256":"8be0228cfb7506b9c28ebd28776c3472b052d53317f4d114b8c09d99ebab3f54"},{"id":"chipswiki-4987-r16133","title":"NetBurst — ChipsWiki, revision 16133","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fnetburst%20(client)&oldid=16133","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/netburst_(client)"],"contentSha256":"335a5161999fc058ac30ceaa1f6cc1abb05f943bf39176ed116bbc99d7fe344f"},{"id":"chipswiki-6347-r19681","title":"Jupiter Sound — ChipsWiki, revision 19681","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fjupiter%20sound&oldid=19681","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/jupiter_sound"],"contentSha256":"f9b0087e8ea311339f04d48ce743d71fe1118d0add49c8654bac2b6256253bff"},{"id":"chipswiki-6405-r20000","title":"Knights Hill — ChipsWiki, revision 20000","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20hill&oldid=20000","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e3/e3-1505l_v6"],"contentSha256":"7b18df979b4b9d3de61cdd11b11733291397df84c4bf928989ed0db61e01d399"},{"id":"chipswiki-7726-r25101","title":"Xeon E5-2686 v4 — ChipsWiki, revision 25101","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2686%20v4&oldid=25101","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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